公开(公告)号：US20210350871A1

公开(公告)日：2021-11-11

申请号：US17382926

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： Jianmin Huang ,  Deping He ,  Xiangang Luo ,  Harish Reddy Singidi ,  Kulachet Tanpairoj ,  Xu Zhang ,  Ting Luo

IPC: G11C29/42 ,  G11C29/14 ,  G11C29/20 ,  G11C29/44 ,  G11C29/00

Abstract: Disclosed in some examples are NAND devices, firmware, systems, methods, and devices that apply smart algorithms to process ECC errors by taking advantage of excess overprovisioning. In some examples, when the amount of overprovisioned blocks are above a predetermined threshold, a first ECC block error handling mode may be implemented and when the overprovisioned blocks are equal or less than the predetermined threshold, a second mode of ECC block error handling may be utilized.

公开(公告)号：US20210073121A1

公开(公告)日：2021-03-11

申请号：US16565066

申请日：2019-09-09

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Qing Liang ,  David Aaron Palmer

IPC: G06F12/02

Abstract: Devices and techniques for a dynamically adjusting a garbage collection workload are described herein. For example, memory device idle times can be recorded. From these recorded idle times, a metric can be derived. A a current garbage collection workload can be divided into portions based on the metric. Then, a first portion of the divided garbage collection workload can be performed at a next idle time.

公开(公告)号：US20180232169A1

公开(公告)日：2018-08-16

申请号：US15749402

申请日：2015-08-20

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4406 ,  G06F11/1068 ,  G11C29/52

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information on stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US20250156316A1

公开(公告)日：2025-05-15

申请号：US19022410

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US20250086055A1

公开(公告)日：2025-03-13

申请号：US18890418

申请日：2024-09-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US20250004939A1

公开(公告)日：2025-01-02

申请号：US18546738

申请日：2023-02-15

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Huachen Li

IPC: G06F12/02

Abstract: Methods, systems, and devices for signal monitoring by a memory system are described. A memory system may receive signaling (e.g., from a host system) and may sample the signal and generate an eye diagram. During a normal mode of operation, the memory system monitor characteristics of the eye diagram to improve signaling. The memory system may determine a voltage level of the signaling based on one or more input parameters and sampling times associated with the signaling. An indication of the voltage level of the signaling may be stored (e.g., to a register of the memory system) and may be periodically transmitted to the host system.

公开(公告)号：US12124322B2

公开(公告)日：2024-10-22

申请号：US17518170

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/073 ,  G06F11/0757 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

公开(公告)号：US12099734B2

公开(公告)日：2024-09-24

申请号：US17846761

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Bo Zhou ,  Caixia Yang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/064 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/0246

Abstract: Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.

公开(公告)号：US12079481B2

公开(公告)日：2024-09-03

申请号：US17898333

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

公开(公告)号：US20240069733A1

公开(公告)日：2024-02-29

申请号：US18233433

申请日：2023-08-14

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Caixia Yang

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. One or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. A first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.