公开(公告)号：US09842847B2

公开(公告)日：2017-12-12

申请号：US14619243

申请日：2015-02-11

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

IPC: H01L27/1156 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

公开(公告)号：US09397210B2

公开(公告)日：2016-07-19

申请号：US14043943

申请日：2013-10-02

Applicant: Micron Technology, Inc.

Inventor： James Mathew ,  Gordon Haller ,  Ronald A. Weimer ,  John Hopkins ,  Vinayak K. Shamanna ,  Sanjeev Sapra

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/764

CPC classification number: H01L29/78 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157

Abstract: A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells.

Abstract translation: 存储器阵列具有半导体上的第一和第二存储器单元以及延伸到半导体中的隔离区。 隔离区包括第一和第二存储单元的电荷存储结构之间的气隙和气隙上的电介质的厚度，并且包含在第一和第二存储单元之间。

公开(公告)号：US08963156B2

公开(公告)日：2015-02-24

申请号：US13774599

申请日：2013-02-22

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

公开(公告)号：US11626424B2

公开(公告)日：2023-04-11

申请号：US17397338

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11563

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US10242995B2

公开(公告)日：2019-03-26

申请号：US15808468

申请日：2017-11-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/302

Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

公开(公告)号：US20180315766A1

公开(公告)日：2018-11-01

申请号：US16028111

申请日：2018-07-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/285 ,  H01L21/311 ,  H01L29/51 ,  H01L29/10 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/31111 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/513 ,  H01L29/66825

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US09281402B2

公开(公告)日：2016-03-08

申请号：US14292443

申请日：2014-05-30

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Gordon Haller

IPC: H01L29/78 ,  H01L21/308 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: There is provided fin methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

Abstract translation: 提供了用于制造翅片结构的翅片方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

公开(公告)号：US20150162246A1

公开(公告)日：2015-06-11

申请号：US14626573

申请日：2015-02-19

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gordon Haller ,  Paul D. Long

IPC: H01L21/8234 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L23/5226 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract translation: 一些实施例包括具有堆叠结构的半导体器件，该堆叠结构包括形成在衬底上的多个交替层的介电材料和多晶硅。 这样的半导体器件还可以包括至少一个具有高纵横比并且延伸到堆叠结构中的开口至与衬底相邻的水平，形成在邻近衬底的开口下部的第一多晶硅沟道，第二聚硅 - 硅沟道，以及设置在开口中的第一多晶硅沟道和第二多晶硅沟道之间的WSiX材料。 WSiX材料与衬底相邻，并且可以用作蚀刻着色层和导电触点，以在开口中接触第一多晶硅沟道和第二多晶硅沟道。 其他实施例包括制造半导体器件的方法。

公开(公告)号：US20130178025A1

公开(公告)日：2013-07-11

申请号：US13781862

申请日：2013-03-01

Applicant: Micron Technology, Inc.

Inventor： Gordon Haller ,  Sanh Dang Tang ,  Steve Cummings

IPC: H01L21/8234

CPC classification number: H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

Abstract: A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Abstract translation: 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。 在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。