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公开(公告)号：US20240071554A1
公开(公告)日：2024-02-29
申请号：US17898725
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Guang Hu
CPC classification number: G11C29/52 , G11C29/022 , G11C29/04 , G11C2029/0407
Abstract: A method includes, in response to detecting a power on event, selecting a block from a set of blocks, causing a first scan to be performed using a set of read level offsets to select, from a set of bins in accordance with a scan order, a first bin assigned with a first read level offset resulting in a first bit error metric value, in response to determining that the first bin is not an initial bin of the scan order, causing, using a second read level offset assigned to a second bin, a second scan to be performed to obtain a second bit error metric value, wherein the second bin immediately precedes the first bin in the scan order, and selecting, based on first bit error metric value and the second bit error metric value, an optimal bin from the set of bins.
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公开(公告)号：US20230205450A1
公开(公告)日：2023-06-29
申请号：US18111213
申请日：2023-02-17
Applicant: Micron Technology, Inc.
Inventor： Chun Sum Yeung , Guang Hu , Ting Luo , Tao Liu
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A method includes performing a first read operation involving a set of memory cells using a first voltage, determining a quantity of bits associated with the set of memory cells based on the first read operation, performing a second read operation involving the set of memory cells using a second voltage that is greater than the first voltage when the quantity of bits is above a threshold quantity of bits for the set of memory cells, and performing the second read operation involving the set of memory cells using a third voltage that is less than the first voltage when the quantity of bits is below the threshold quantity of bits for the set of memory cells.
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公开(公告)号：US20220276928A1
公开(公告)日：2022-09-01
申请号：US17746754
申请日：2022-05-17
Applicant: Micron Technology, Inc.
Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.
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公开(公告)号：US11340982B1
公开(公告)日：2022-05-24
申请号：US17087334
申请日：2020-11-02
Applicant: Micron Technology, Inc.
Abstract: An apparatus includes a memory sub-system comprising a plurality of memory blocks and a memory block defect detection component. The memory block defect detection component is to set, for a memory block among the plurality of memory blocks, a first block defect detection rate and determine whether the first block defect detection rate is greater than a threshold block defect detection rate for the at least one memory block. In response to a determination that the first block defect detection rate is greater than the threshold block defect detection rate for the memory block, the memory block defect detection component is to assert a program command on the memory block determine whether a program operation associated with assertion of the program command on the at least one memory block is successful. In response to a determination the program operation is unsuccessful, the memory block defect detection component is to determine that a failure involving a plane associated with the memory block and another plane of the memory sub-system has occurred.
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公开(公告)号：US12242734B2
公开(公告)日：2025-03-04
申请号：US18237668
申请日：2023-08-24
Applicant: Micron Technology, Inc.
IPC: G06F3/06
Abstract: A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.
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Patent Agency Ranking
公开(公告)号：US20250006292A1
公开(公告)日：2025-01-02
申请号：US18440619
申请日：2024-02-13
Applicant: Micron Technology, Inc.
Inventor： Taylor Alu , Nicola Ciocchini , Shyam Sunder Raghunathan , Guang Hu , Walter Di Francesco , Umberto Siciliani , Violante Moschiano , Karan Banerjee
Abstract: A method includes detecting a change in a memory control signal of a memory device including memory blocks, determining based at least on the change in the memory control signal that the memory device is in a stable state, and responsive to determining that the memory device is in the stable state, associating a voltage offset bin with at least one memory block of the memory device.
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公开(公告)号：US20240256444A1
公开(公告)日：2024-08-01
申请号：US18411940
申请日：2024-01-12
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Guang Hu , Xianganfg Luo , Jung Sheng Hoei , Ting Luo , Zhenming Zhou , Jianmin Huang
IPC: G06F12/06
CPC classification number: G06F12/0607
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. The controller identifies a first partial good block (PGB) in a set of memory components, the first PGB having first subset of word line groups (WGRs) that are categorized as being non-defective. The controller searches for a second PGB in the set of memory components having a second subset of WGRs that are categorized as being non-defective. The controller computes a total quantity of WGRs based on the first quantity of WGRs in the first subset of WGRs and a second quantity of WGRs in the second subset of WGRs and, in response, combines the first PGB and the second PGB to form an individual virtual block.
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公开(公告)号：US12027213B2
公开(公告)日：2024-07-02
申请号：US17637766
申请日：2021-03-19
Applicant: Micron Technology, Inc.
Inventor： Jie Zhou , Xiangang Luo , Min Rui Ma , Guang Hu
CPC classification number: G11C16/26 , G11C29/028 , G11C29/52
Abstract: Methods, systems, and devices for determining offsets for memory read operations are described. In response to a threshold quantity of pages failing initial reads but being successfully read using a same reference adjustment during re-reads, the offset responsible for the adjustment may be used as a first-applied offset for subsequent re-reads or a baseline offset for subsequent initial reads. After the initial reads begin using the reference adjustment, if a threshold quantity of pages fail initial reads, the offset used for the initial read may be adjusted to be the offset used to perform the successful re-reads. If an updated offset to use a baseline is not identified, the baseline offset may be cleared so the original reference may again be used without adjustment for initial reads.
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公开(公告)号：US20240086079A1
公开(公告)日：2024-03-14
申请号：US18237668
申请日：2023-08-24
Applicant: Micron Technology, Inc.
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0634 , G06F3/0679
Abstract: A system comprises a memory device including a plurality of management units and a processing device. The processing device is operatively coupled with the memory device and configured to place the plurality of management units into a first protective state by erasing the plurality of management units, identify a cursor satisfying a cursor definition, identify a subset of the plurality of management units based on a location, on the memory device, referenced by the cursor, and place a selected management unit of the subset of the plurality of management units into a second protective state by programming a protective data pattern to the selected management unit.
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公开(公告)号：US11900992B2
公开(公告)日：2024-02-13
申请号：US17649885
申请日：2022-02-03
Applicant: Micron Technology, Inc.
IPC: G11C16/04 , G11C11/4099 , G11C11/4074 , G11C11/4096 , G11C11/4076 , G11C11/408
CPC classification number: G11C11/4099 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4096
Abstract: Methods, systems, and devices for reference voltage adjustment for word line groups are described. In some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. Based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. For example, a voltage value of one or more reference voltages may be adjusted based on the duration. Moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. The adjusted reference voltages may be used during a subsequent read operation. The voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.
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