公开(公告)号：US09627251B2

公开(公告)日：2017-04-18

申请号：US14722889

申请日：2015-05-27

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11521

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

公开(公告)号：US09570681B2

公开(公告)日：2017-02-14

申请号：US14491713

申请日：2014-09-19

Applicant: Micron Technology, Inc.

Inventor： Cristina Casellato ,  Carmela Cupeta ,  Michele Magistretti ,  Fabio Pellizzer ,  Roberto Somaschini

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24 ,  H01L23/532 ,  H01L27/10

CPC classification number: H01L45/16 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract translation: 电阻随机存取存储器可以包括存储器阵列和围绕存储器阵列的周边。 外围的解码器可以通过使用相同的金属沉积在同一时间在周边和阵列中形成金属化而耦合到阵列中的地址线。 金属化可以在阵列中形成行线。

公开(公告)号：US09246100B2

公开(公告)日：2016-01-26

申请号：US13949315

申请日：2013-07-24

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini ,  Gabriel L. Donadio

IPC: H01L45/00 ,  G11C5/06 ,  G11C13/00

CPC classification number: H01L27/2481 ,  G11C5/063 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

Abstract translation: 本公开包括存储单元阵列结构及其形成方法。 一种这样的阵列包括堆叠结构，其包括在第一导电材料和第二导电材料之间的存储单元。 存储器单元可以包括选择元件和存储元件。 阵列还可以包括位于堆叠结构的边缘处的电惰性堆叠结构。

公开(公告)号：US09059261B2

公开(公告)日：2015-06-16

申请号：US14302160

申请日：2014-06-11

Applicant: Micron Technology, Inc.

Inventor： Roberto Somaschini ,  Alessandro Vaccaro ,  Paolo Tessariol ,  Giulio Albini

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/522 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1052 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract translation: 半导体存储器的阵列触点可以使用第一组并行条纹掩模形成，随后可以与第一组横向的第二组平行条纹掩模形成。 例如，可以使用一组掩模来蚀刻介电层，以形成平行隔开的沟槽。 然后可以用牺牲材料填充沟槽。 然后，该牺牲材料可以横向于其长度被掩蔽并被蚀刻。 所得到的开口可以用金属填充以形成阵列触点。

公开(公告)号：US20150044832A1

公开(公告)日：2015-02-12

申请号：US14491713

申请日：2014-09-19

Applicant: Micron Technology, Inc.

Inventor： Cristina Casellato ,  Carmela Cupeta ,  Michele Magistretti ,  Fabio Pellizzer ,  Roberto Somaschini

IPC: H01L45/00 ,  H01L23/528 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L23/5283 ,  H01L23/53295 ,  H01L27/101 ,  H01L27/24 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Abstract translation: 电阻随机存取存储器可以包括存储器阵列和围绕存储器阵列的周边。 外围的解码器可以通过使用相同的金属沉积在同一时间在周边和阵列中形成金属化而耦合到阵列中的地址线。 金属化可以在阵列中形成行线。

公开(公告)号：US20150029775A1

公开(公告)日：2015-01-29

申请号：US13949315

申请日：2013-07-24

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini ,  Gabriel L. Donadio

IPC: G11C5/06 ,  G11C13/00 ,  H01L45/00

CPC classification number: H01L27/2481 ,  G11C5/063 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

Abstract: The present disclosure includes memory cell array structures and methods of forming the same. One such array includes a stack structure comprising a memory cell between a first conductive material and a second conductive material. The memory cell can include a select element and a memory element. The array can also include an electrically inactive stack structure located at an edge of the stack structure.

Abstract translation: 本公开内容包括存储单元阵列结构及其形成方法。 一种这样的阵列包括堆叠结构，其包括在第一导电材料和第二导电材料之间的存储单元。 存储器单元可以包括选择元件和存储元件。 阵列还可以包括位于堆叠结构的边缘处的电惰性堆叠结构。

公开(公告)号：US10910437B2

公开(公告)日：2021-02-02

申请号：US16420483

申请日：2019-05-23

Applicant: Micron Technology, Inc.

Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

IPC: H01L27/24 ,  H01L45/00

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

公开(公告)号：US20190067372A1

公开(公告)日：2019-02-28

申请号：US16112570

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Ombretta Donghi ,  Marcello Ravasio ,  Samuele Sciarrillo ,  Roberto Somaschini

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: A method of fabricating a memory device is disclosed. In one aspect, the method comprises patterning a first conductive line extending in a first direction. The method additionally includes forming a free-standing pillar of a memory cell stack on the first conductive line after patterning the first conductive line. Forming the free-standing pillar includes depositing a memory cell stack comprising a selector material and a storage material over the conductive line and patterning the memory cell stack to form the free-standing pillar. The method further includes patterning a second conductive line on the pillar after patterning the memory cell stack, the second conductive line extending in a second direction crossing the first direction.

公开(公告)号：US09806129B2

公开(公告)日：2017-10-31

申请号：US14189490

申请日：2014-02-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Roberto Somaschini ,  Cristina Casellato ,  Riccardo Mottadelli

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2463 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a method of fabricating cross-point memory arrays comprises forming a memory cell material stack which includes a first active material and a second active material over the first active material, wherein one of the first and second active materials comprises a storage material and the other of the first and second active materials comprises a selector material. The method of fabricating cross-point arrays further comprises patterning the memory cell material stack, which includes etching through at least one of the first and second active materials of the memory cell material stack, forming protective liners on sidewalls of the at least one of the first and second active materials after etching through the one of the first and second active materials, and further etching the memory cell material stack after forming the protective liners on the sidewalls of the one of the first and second active materials.

公开(公告)号：US20160181156A1

公开(公告)日：2016-06-23

申请号：US15000935

申请日：2016-01-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Antonino Rigano ,  Roberto Somaschini

IPC: H01L21/768 ,  H01L45/00 ,  H01L23/522 ,  H01L27/24

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures provide horizontal conductive lines of fine pitch and self-aligned contacts extending from them, where the contacts have at least one dimension with a more relaxed pitch. Buried hard mask materials permit self-alignment of the lines and contacts without a critical mask, such as for word-line electrode lines and word-line contacts in a memory device.

Abstract translation: 方法和结构提供了从它们延伸的细间距和自对准触点的水平导线，其中触点具有至少一个具有更宽松间距的尺寸。 掩埋硬掩模材料允许线和触点的自对准，而不需要临界掩模，例如用于存储器件中的字线电极线和字线接触。