公开(公告)号：US20250069638A1

公开(公告)日：2025-02-27

申请号：US18944400

申请日：2024-11-12

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Joo-Sang Lee ,  Scott E. Smith

IPC: G11C11/406 ,  G11C11/4074

Abstract: Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

公开(公告)号：US20240420746A1

公开(公告)日：2024-12-19

申请号：US18814826

申请日：2024-08-26

Applicant: Micron Technology, Inc.

Inventor： Brian W. Huber ,  Scott E. Smith ,  Gary L. Howe

IPC: G11C7/10

Abstract: A memory device includes a command interface configured to receive write commands from a host device. Additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. Furthermore, the memory device includes a first ripple counter and a second ripple counter. The memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. The command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.

公开(公告)号：US12068021B2

公开(公告)日：2024-08-20

申请号：US17746757

申请日：2022-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Noriaki Mochida ,  Takayuki Miyamoto ,  Kallol Mazumder ,  Scott E. Smith

IPC: G11C11/4076 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C11/4093

Abstract: An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

公开(公告)号：US20240161855A1

公开(公告)日：2024-05-16

申请号：US18504215

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Sujeet Ayyapureddi

IPC: G11C29/42

CPC classification number: G11C29/42

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

公开(公告)号：US20240160527A1

公开(公告)日：2024-05-16

申请号：US18504316

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016 ,  G06F11/1024

Abstract: Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

公开(公告)号：US20240078153A1

公开(公告)日：2024-03-07

申请号：US18313670

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/102 ,  G06F11/1032

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US20230395116A1

公开(公告)日：2023-12-07

申请号：US18202149

申请日：2023-05-25

Applicant: Micron Technology, Inc.

Inventor： Anthony D. Veches ,  Scott E. Smith

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.

公开(公告)号：US20230367709A1

公开(公告)日：2023-11-16

申请号：US18144655

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Scott E. Smith ,  Matthew A. Prather ,  Erik V. Pohlmann

IPC: G06F12/06 ,  G06F11/07

CPC classification number: G06F12/06 ,  G06F11/0727 ,  G06F2212/1032

Abstract: Methods, systems, and devices for write command timing enhancement are described. A host device may transmit (e.g., issue), to a memory device, an activation command and an associated write command according to a delay that is different (e.g., shorter) than a row access to column access delay associated with read commands. In some examples, the delay between the activation command and the associated write command may be a function of the row access to column access delay associated with read commands and one or more additional parameters, such as a timing constraint or a speed parameter of the memory device.

公开(公告)号：US20230146544A1

公开(公告)日：2023-05-11

申请号：US17523312

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Mijo Kim ,  Scott E. Smith ,  Si Hong Kim

IPC: G11C7/10 ,  G11C7/20 ,  G11C8/18

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C7/20 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/18

Abstract: Memory with DQS pulse control circuitry is disclosed herein. In one embodiment, a memory device comprises a DQS terminal and circuitry operably coupled to the DQS terminal. The DQS terminal is configured to receive an external DQS signal including a first pulse having a first width. In turn, the circuitry is configured to generate a second pulse based at least in part on the first pulse and output an internal DQS signal including the second pulse. The second pulse can have a second width greater than the first width. In some embodiments, the external DQS signal can further include a third pulse having a third width greater than the second width. In such embodiments, the circuitry can be further configured to generate and output a fourth pulse based at least in part on the third pulse that has a fourth width equivalent to the third width.

公开(公告)号：US11487610B2

公开(公告)日：2022-11-01

申请号：US15975703

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： William C. Waldrop ,  Vijayakrishna J. Vankayala ,  Scott E. Smith

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42

Abstract: Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.