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公开(公告)号：US12205653B2
公开(公告)日：2025-01-21
申请号：US18083304
申请日：2022-12-16
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Shyam Sunder Raghunathan , Walter Di Francesco
Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.
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公开(公告)号：US20240379176A1
公开(公告)日：2024-11-14
申请号：US18781317
申请日：2024-07-23
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Shyam Sunder Raghunathan , Haiou Che , Walter di Francesco
Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
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公开(公告)号：US20240339163A1
公开(公告)日：2024-10-10
申请号：US18604411
申请日：2024-03-13
Applicant: Micron Technology, Inc.
Inventor： Leo Raimondo , Violante Moschiano , Shyam Sunder Raghunathan , Akira Goda
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/10
Abstract: Control logic in a memory device initiates a program operation on a memory array comprising a top deck and bottom deck. During a seeding phase of the program operation, the control logic causes a first positive voltage to be applied to a first plurality of wordlines of the memory array, wherein the first plurality of wordlines is associated with memory cells in the bottom deck of the memory array that are in a programmed state, and causes a ground voltage to be applied to a second plurality of wordlines of the memory array, wherein the second plurality of wordlines is associated with memory cells in the top deck of the memory array. At an end of the seeding phase of the program operation, the control logic electrically separates the top deck from the bottom deck and causes a program voltage to be applied to a selected wordline of the memory array during an inhibit phase of the program operation, wherein the selected wordline is associated with respective memory cells in the top deck of the memory array.
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公开(公告)号：US12087372B2
公开(公告)日：2024-09-10
申请号：US17845394
申请日：2022-06-21
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Shyam Sunder Raghunathan , Haiou Che , Walter di Francesco
CPC classification number: G11C16/3445 , G11C16/16
Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
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Patent Agency Ranking
公开(公告)号：US20240062829A1
公开(公告)日：2024-02-22
申请号：US17888781
申请日：2022-08-16
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Karan Banerjee , Shyam Sunder Raghunathan
IPC: G11C16/26
CPC classification number: G11C16/26
Abstract: Methods, systems, and devices for transient and stable state read operations of a memory device are described. A memory system may implement a read operation including a delay if a channel is at stable state, and may implement a read operation without a delay if the channel is in a transient state. Upon receiving a read command to a set of memory cells sharing the channel, the memory system may determine whether the channel is in a stable or transient state. If the channel is in a stable state, the memory system may perform a read operation including a delay between boosting the channel and driving respective word lines, such that the channel partially discharges prior to driving the word lines. If the channel is in a transient state, the memory system may perform a read operation without a delay between boosting the channel and driving the word lines.
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公开(公告)号：US11762767B2
公开(公告)日：2023-09-19
申请号：US17302064
申请日：2021-04-22
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Giuseppina Puzzilli , Vamsi Pavan Rayaprolu , Ashutosh Malshe , James Fitzpatrick , Shyam Sunder Raghunathan , Violante Moschiano , Tecla Ghilardi
CPC classification number: G06F12/0269 , G11C16/3418 , G11C29/52 , G06F2212/702 , G11C16/0483
Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.
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公开(公告)号：US20220415414A1
公开(公告)日：2022-12-29
申请号：US17845394
申请日：2022-06-21
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Shyam Sunder Raghunathan , Haiou Che , Walter di Francesco
Abstract: Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
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公开(公告)号：US20160307622A1
公开(公告)日：2016-10-20
申请号：US15189178
申请日：2016-06-22
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shyam Sunder Raghunathan , Pranav Kalavade , Krishna K. Parat , Charan Srinivasan
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
Abstract: Methods of operating a memory include applying a multi-step pass voltage to a plurality of memory cells selected for a programming operation, applying a programming pulse to the plurality of memory cells selected for the programming operation after applying a voltage level of a particular step of the multi-step pass voltage to the plurality of memory cells selected for the programming operation, applying a particular voltage level to any data lines coupled to a first subset of memory cells of the plurality of memory cells selected for the programming operation prior to applying a voltage level of a certain step of the multi-step pass voltage, and applying the particular voltage level to any data lines coupled to a second subset of memory cells of the plurality of memory cells selected for the programming operation only after applying the voltage level of the certain step of the multi-step pass voltage.
Abstract translation: 操作存储器的方法包括对选择用于编程操作的多个存储器单元施加多级通过电压，在将编程脉冲施加到编程操作所选择的多个存储器单元之后，施加特定步骤的电压电平 向被选择用于编程操作的多个存储器单元的多步通过电压，将特定电压电平施加到耦合到在应用编程操作之前被选择用于编程操作的多个存储器单元中的存储器单元的第一子集的任何数据线 多级通过电压的某一步骤的电压电平，并且将特定电压电平施加到仅在施加电压电平之后耦合到被选择用于编程操作的多个存储器单元的存储器单元的第二子集的任何数据线 多步通过电压的一定步骤。
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公开(公告)号：US20160019949A1
公开(公告)日：2016-01-21
申请号：US14334946
申请日：2014-07-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shyam Sunder Raghunathan , Pranav Kalavade , Krishna K. Parat , Charan Srinivasan
CPC classification number: G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3427
Abstract: Memories and methods for programming memories with multi-level pass signals are provided. One method includes programming cells of the memory selected to be programmed to a particular target data state of the memory, using program disturb to program cells of the memory selected to be programmed to target data states that are lower than the particular target data state while programming cells of the memory selected to be programmed to the particular target data state, and boosting a channel voltage for cells of the memory selected to be programmed to the target data states that are lower than the particular target data state. Boosting may include using a multi-step pass signal.
Abstract translation: 提供了用于编程具有多级通过信号的存储器的存储器和方法。 一种方法包括将选择要编程的存储器的单元编程为存储器的特定目标数据状态，使用程序干扰来编程选择要编程的存储器的单元，以在编程期间将目标数据状态低于特定目标数据状态 将存储器的单元选择为被编程到特定目标数据状态，以及将选择要编程的存储器的单元的通道电压提升到低于特定目标数据状态的目标数据状态。 升压可能包括使用多步通过信号。
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