Transistors having one or more dummy lines with different collective widths coupled thereto
    21.
    发明授权
    Transistors having one or more dummy lines with different collective widths coupled thereto 有权
    晶体管具有一个或多个具有与其相连的不同总宽度的虚线

    公开(公告)号:US09287260B1

    公开(公告)日:2016-03-15

    申请号:US14478220

    申请日:2014-09-05

    Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

    Abstract translation: 在一个实施例中,晶体管阵列具有耦合到第一晶体管的第一线。 第一行延伸在与第一晶体管相连的第二晶体管上,以及连续相邻于第二晶体管的第三晶体管。 第二线耦合到第二晶体管并在第三晶体管上延伸。 一个或多个第一虚拟线耦合到第一线并且从第一晶体管延伸到第二晶体管。 一个或多个第二虚拟线耦合到第二线并且从第二晶体管延伸到第三晶体管。 一个或多个第一虚拟线的总体宽度大于一个或多个第二虚拟线的总体宽度。

    Methods of forming capacitor structures

    公开(公告)号:US11569221B2

    公开(公告)日:2023-01-31

    申请号:US17358251

    申请日:2021-06-25

    Abstract: Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

    APPARATUS HAVING INTEGRATED CIRCUIT WELL STRUCTURES OF VERTICAL AND/OR RETROGRADE PROFILES

    公开(公告)号:US20200303192A1

    公开(公告)日:2020-09-24

    申请号:US16899715

    申请日:2020-06-12

    Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.

    TRANSISTORS HAVING ONE OR MORE DUMMY LINES WITH DIFFERENT COLLECTIVE WIDTHS COUPLED THERETO
    29.
    发明申请
    TRANSISTORS HAVING ONE OR MORE DUMMY LINES WITH DIFFERENT COLLECTIVE WIDTHS COUPLED THERETO 有权
    带有不同组合宽度的一个或多个DUMMY线的晶体管

    公开(公告)号:US20160071842A1

    公开(公告)日:2016-03-10

    申请号:US14478220

    申请日:2014-09-05

    Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

    Abstract translation: 在一个实施例中,晶体管阵列具有耦合到第一晶体管的第一线。 第一行延伸在与第一晶体管相连的第二晶体管上,以及连续相邻于第二晶体管的第三晶体管。 第二线耦合到第二晶体管并在第三晶体管上延伸。 一个或多个第一虚拟线耦合到第一线并且从第一晶体管延伸到第二晶体管。 一个或多个第二虚拟线耦合到第二线并且从第二晶体管延伸到第三晶体管。 一个或多个第一虚拟线的总体宽度大于一个或多个第二虚拟线的总体宽度。

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