公开(公告)号：US09287260B1

公开(公告)日：2016-03-15

申请号：US14478220

申请日：2014-09-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: H01L27/088 ,  H01L27/115 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/11578 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

Abstract translation: 在一个实施例中，晶体管阵列具有耦合到第一晶体管的第一线。 第一行延伸在与第一晶体管相连的第二晶体管上，以及连续相邻于第二晶体管的第三晶体管。 第二线耦合到第二晶体管并在第三晶体管上延伸。 一个或多个第一虚拟线耦合到第一线并且从第一晶体管延伸到第二晶体管。 一个或多个第二虚拟线耦合到第二线并且从第二晶体管延伸到第三晶体管。 一个或多个第一虚拟线的总体宽度大于一个或多个第二虚拟线的总体宽度。

公开(公告)号：US11935883B2

公开(公告)日：2024-03-19

申请号：US18096222

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Michael Violette

IPC: H01L27/02 ,  G11C7/24 ,  G11C16/04 ,  G11C16/30 ,  H01L23/60 ,  H01L23/62 ,  H01L29/45 ,  H01L29/866 ,  H01L49/02 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L27/0248 ,  G11C7/24 ,  G11C16/0483 ,  G11C16/30 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0292 ,  H01L28/60 ,  H01L29/456 ,  H01L29/866 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

Abstract: Capacitor structures, and apparatus containing similar capacitor structures, might include a first conductive region having a first portion and second and third portions extending from an upper surface of its first portion, a second conductive region having a first portion and a second portion extending from an upper surface of its first portion, a dielectric overlying the second portion of the first conductive region, a conductor overlying the dielectric, and a conductive element overlying the third portion of the first conductive region and overlying the second portion of the second conductive region, wherein the first conductive region has a first conductivity type and the second conductive region has a second conductivity type different than the first conductivity type.

公开(公告)号：US20230170344A1

公开(公告)日：2023-06-01

申请号：US18096222

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Michael Violette

IPC: H01L27/02 ,  H01L29/866 ,  H01L29/45 ,  G11C16/30 ,  G11C16/04 ,  H01L23/60 ,  H01L23/62 ,  G11C7/24 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

CPC classification number: H01L27/0248 ,  H01L28/60 ,  H01L29/866 ,  H01L29/456 ,  G11C16/30 ,  G11C16/0483 ,  H01L23/60 ,  H01L23/62 ,  G11C7/24 ,  H01L27/0292 ,  H10B41/20 ,  H10B41/40 ,  H10B43/20 ,  H10B43/40

Abstract: Capacitor structures, and apparatus containing similar capacitor structures, might include a first conductive region having a first portion and second and third portions extending from an upper surface of its first portion, a second conductive region having a first portion and a second portion extending from an upper surface of its first portion, a dielectric overlying the second portion of the first conductive region, a conductor overlying the dielectric, and a conductive element overlying the third portion of the first conductive region and overlying the second portion of the second conductive region, wherein the first conductive region has a first conductivity type and the second conductive region has a second conductivity type different than the first conductivity type.

公开(公告)号：US20230162792A1

公开(公告)日：2023-05-25

申请号：US18095025

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Haitao Liu

IPC: G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H01L29/42328 ,  H01L29/66484 ,  H01L29/7926 ,  H01L29/7889 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Transistors, and memories including such transistors, might include an active area having a first conductivity type, first and second source/drain regions in the active area and having a second conductivity type, and a plurality of control gates between the first and second source/drain regions and the second source/drain region, wherein each control gate of the plurality of control gates includes a respective first control gate portion overlying a first side of the active area, and a respective second control gate portion connected to its respective first control gate portion that is either adjacent to a second side of the active area orthogonal to the first side of the active area, or underlying a second side of the active area opposite the first side of the active area.

公开(公告)号：US11569221B2

公开(公告)日：2023-01-31

申请号：US17358251

申请日：2021-06-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Michael Violette

IPC: H01L27/02 ,  H01L49/02 ,  H01L29/866 ,  H01L27/11526 ,  H01L29/45 ,  G11C16/30 ,  H01L27/11578 ,  H01L27/11551 ,  G11C16/04 ,  H01L27/11573 ,  H01L23/60 ,  H01L23/62 ,  G11C7/24

Abstract: Methods of forming a capacitor structure might include forming a first and second conductive regions having first and second conductivity types, respectively, in a semiconductor material, forming a dielectric overlying the first and second conductive regions, forming a conductor overlying the dielectric, and patterning the conductor, the dielectric, and the first and second conductive regions to form a first island of the first conductive region, a second island of the first conductive region, an island of the second conductive region, a first portion of the dielectric overlying the first island of the first conductive region separated from a second portion of the dielectric overlying the second island of the first conductive region and the island of the second conductive region, and a first portion of the conductor overlying the first portion of the dielectric separated from a second portion of the conductor overlying the second portion of the dielectric.

公开(公告)号：US11568934B2

公开(公告)日：2023-01-31

申请号：US17223482

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vladimir Mikhalev ,  Haitao Liu

IPC: H01L27/11556 ,  H01L29/66 ,  G11C16/04 ,  H01L29/423 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/788 ,  H01L21/28 ,  H01L27/11519

Abstract: Multi-gate transistors, as well as apparatus containing such multi-gate transistors and methods of forming such multi-gate transistors, might facilitate gating voltages in integrated circuit devices. Such multi-gate transistors might include an active area having a first conductivity type, a first source/drain region in the active area and having a second conductivity type different than the first conductivity type, a second source/drain region in the active area and having the second conductivity type, and a plurality of control gates adjacent the active area between the first source/drain region and the second source/drain region, wherein each control gate of the plurality of control gates comprises a respective plurality of control gate portions, and wherein, for a particular control gate of the plurality of control gates, each control gate portion of its respective plurality of control gate portions is adjacent the active area in a respective plane of a plurality of different planes.

公开(公告)号：US20200303192A1

公开(公告)日：2020-09-24

申请号：US16899715

申请日：2020-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Violette ,  Vladimir Mikhalev

IPC: H01L21/266 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66

Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.

公开(公告)号：US20160336276A1

公开(公告)日：2016-11-17

申请号：US15218888

申请日：2016-07-25

Applicant: Micron Technology, Inc.

Inventor： Vladimir Mikhalev ,  Michael Smith ,  Henry J. Fulford ,  Puneet Sharma ,  Zia A. Shafi

IPC: H01L23/552 ,  H03K17/16 ,  H01L29/78 ,  H01L23/532 ,  H01L29/40 ,  H01L23/522

CPC classification number: H01L23/552 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/088 ,  H01L29/402 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7833 ,  H01L2924/0002 ,  H03K17/161 ,  H03K17/162 ,  H01L2924/00

Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

公开(公告)号：US20160071842A1

公开(公告)日：2016-03-10

申请号：US14478220

申请日：2014-09-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Vladimir Mikhalev

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L27/115

CPC classification number: H01L27/11578 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: In an embodiment, an array of transistors has a first line coupled to a first transistor. The first line extends over a second transistor that is successively adjacent to the first transistor and over a third transistor that is successively adjacent to the second transistor. A second line is coupled to the second transistor and extends over the third transistor. One or more first dummy lines are coupled to the first line and extend from the first transistor to the second transistor. One or more second dummy lines are coupled to the second line and extend from the second transistor to the third transistor. A collective width of the one or more first dummy lines is greater than a collective width of the one or more second dummy lines.

Abstract translation: 在一个实施例中，晶体管阵列具有耦合到第一晶体管的第一线。 第一行延伸在与第一晶体管相连的第二晶体管上，以及连续相邻于第二晶体管的第三晶体管。 第二线耦合到第二晶体管并在第三晶体管上延伸。 一个或多个第一虚拟线耦合到第一线并且从第一晶体管延伸到第二晶体管。 一个或多个第二虚拟线耦合到第二线并且从第二晶体管延伸到第三晶体管。 一个或多个第一虚拟线的总体宽度大于一个或多个第二虚拟线的总体宽度。