公开(公告)号：US10284186B2

公开(公告)日：2019-05-07

申请号：US15704868

申请日：2017-09-14

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma

IPC: H03K5/156 ,  H03K5/15 ,  H03K19/003 ,  H03K5/00 ,  H03K19/013

Abstract: Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.

公开(公告)号：US20180367130A1

公开(公告)日：2018-12-20

申请号：US15622739

申请日：2017-06-14

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma

IPC: H03K5/15 ,  H03D7/14

CPC classification number: H03K5/15046 ,  H03D7/1483 ,  H03K2005/00058

Abstract: Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signals separated in phase by a constructed amount of phase based on the specified mixing ratio. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20180336940A1

公开(公告)日：2018-11-22

申请号：US16037546

申请日：2018-07-17

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma ,  Huy T. Vo

IPC: G11C7/22 ,  G11C7/20 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/20 ,  G11C2207/2254

Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.

公开(公告)号：US20180241383A1

公开(公告)日：2018-08-23

申请号：US15956601

申请日：2018-04-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yantao Ma

IPC: H03K5/156

CPC classification number: H03K5/1565

Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.

公开(公告)号：US20180123574A1

公开(公告)日：2018-05-03

申请号：US15856244

申请日：2017-12-28

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma

IPC: H03K5/15 ,  G11C8/10 ,  H03D7/16 ,  G11C7/22

CPC classification number: H03K5/15013 ,  G11C7/20 ,  G11C7/222 ,  G11C8/10 ,  G11C11/4072 ,  G11C11/4076 ,  H03B27/00 ,  H03D7/165

Abstract: Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.

公开(公告)号：US09954517B2

公开(公告)日：2018-04-24

申请号：US13670222

申请日：2012-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yantao Ma

IPC: H03K5/06 ,  H03K5/156

CPC classification number: H03K5/1565

Abstract: Apparatuses, duty cycle adjustment circuits, adjustment circuits, and methods for duty cycle adjustment are disclosed herein. An example duty cycle adjustment circuit may be configured to receive a signal and adjust a duty cycle of the signal a first amount using a coarse adjustment. The duty cycle adjustment circuit may further be configured, after adjusting the duty cycle of the signal a first amount, to adjust the duty cycle of the signal a second amount different from the first amount using a fine adjustment to provide a duty cycle adjusted signal.

公开(公告)号：US09673793B2

公开(公告)日：2017-06-06

申请号：US14806538

申请日：2015-07-22

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma

IPC: H03K5/12 ,  H03K5/05 ,  H03K5/156

CPC classification number: H03K5/12 ,  H03K5/05 ,  H03K5/134 ,  H03K5/1565

Abstract: Apparatuses and methods for adjusting timing of signals are described herein. An example method may include providing an output clock signal responsive to an input clock signal, and adjusting a slew rate of the output clock signal by a delayed output clock signal.

公开(公告)号：US09584140B2

公开(公告)日：2017-02-28

申请号：US14576614

申请日：2014-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yantao Ma ,  Tyler Gomm

IPC: H03L7/06 ,  H03L7/085 ,  G11C7/22 ,  H03H11/26 ,  H03L7/081 ,  H03K5/14

CPC classification number: H03L7/085 ,  G11C7/222 ,  H03H11/265 ,  H03K5/14 ,  H03L7/0818

Abstract: Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.

Abstract translation: 描述用于延迟信号的装置，方法和延迟电路。 示例性装置包括精细延迟电路，其被配置为基于第一输入信号和第二输入信号的比率来提供输出信号。 该微型延迟电路包括相位混合电路，该相位混合电路包括被配置为接收第一输入信号的第一信号驱动器。 精细延迟电路还包括被配置为接收第二输入信号的第二信号驱动器，其中至少两个第一信号驱动器具有不同的驱动强度，并且至少两个第二信号驱动器具有不同的驱动强度。

公开(公告)号：US09413338B2

公开(公告)日：2016-08-09

申请号：US14285328

申请日：2014-05-22

Applicant: Micron Technology, Inc.

Inventor： Yantao Ma

IPC: H03K3/017 ,  H03K3/037 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K3/037 ,  H03K5/1565

Abstract: Apparatuses, methods, and duty cycle correction circuits are described. An example apparatus includes a duty cycle correction (DCC) adjustment circuit configured to receive an input signal, and to adjust a duty cycle of the input signal to provide an output signal. The DCC circuit including a coarse adjust control circuit configured to adjust the duty cycle of the input signal by a first amount that is equal to one or more unit adjustments, and a fine adjust control circuit that is configured to adjust the duty cycle of the input signal responsive to a pulse signal by a second amount that is less than the unit adjustment.

Abstract translation: 描述了装置，方法和占空比校正电路。 示例性装置包括配置为接收输入信号并且调整输入信号的占空比以提供输出信号的占空比校正（DCC）调整电路。 所述DCC电路包括：粗调整控制电路，被配置为将所述输入信号的占空比调整为等于一个或多个单位调整的第一量;以及微调控制电路，其被配置为调整所述输入的占空比 响应于脉冲信号的信号小于单位调整的第二量。

公开(公告)号：US09331702B2

公开(公告)日：2016-05-03

申请号：US14622031

申请日：2015-02-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yantao Ma ,  Tyler Gomm

IPC: G11C7/00 ,  H03L7/08 ,  G11C7/22 ,  H03L7/081

CPC classification number: H03L7/0802 ,  G11C7/222 ,  H03L7/0812 ,  H03L2207/04

Abstract: Apparatuses and methods for compensating for differing power supply sensitivities of a circuit in a clock path. One such method includes altering signal timing of at least one of reference and feedback clock signals differently according to variations in power supply voltage to compensate for differences in delay power supply sensitivities of delays of a forward clock path and of a feedback clock path. Another example method includes providing an output clock signal in phase with an input clock signal and compensating for delay error between delays used in providing at least some of the delay of the output clock signal relative to the input clock signal by providing delays having power supply sensitivities resulting in a combined power supply sensitivity that is inverse to the delay error.