公开(公告)号：US20130102111A1

公开(公告)日：2013-04-25

申请号：US13713320

申请日：2012-12-13

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: H01L21/50

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  H01L21/50 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).

Abstract translation: 公开了一种包括非易失性存储器件的堆叠。 堆栈中的非易失性存储器件之一是主器件，而其余存储器件或器件是从器件。

公开(公告)号：US20130033941A1

公开(公告)日：2013-02-07

申请号：US13649403

申请日：2012-10-11

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/10

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract translation: 存储器件包括诸如用于存储数据的闪存的核心存储器。 存储器件包括用于接收用于为闪速存储器供电的第一电压的第一电源输入。 另外，存储器件包括用于接收第二电压的第二电源输入。 存储器件包括被配置为接收第二电压并导出一个或多个内部电压的电源管理电路。 电源管理电路将内部电压提供或传送到闪存。 由功率管理电路（例如，电压转换器电路）产生并提供给核心存储器的不同的内部电压使得诸如针对核心存储器中的单元的读取/编程/擦除的操作。

公开(公告)号：US09263146B2

公开(公告)日：2016-02-16

申请号：US14208812

申请日：2014-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki Kim

IPC: G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

公开(公告)号：US09257193B2

公开(公告)日：2016-02-09

申请号：US14156047

申请日：2014-01-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09245640B2

公开(公告)日：2016-01-26

申请号：US14107735

申请日：2013-12-16

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/10 ,  G11C16/30 ,  G11C5/14 ,  G11C16/12 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US08767461B2

公开(公告)日：2014-07-01

申请号：US14022805

申请日：2013-09-10

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: G11C16/04

CPC classification number: G11C16/06 ,  G06F12/0246 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Abstract translation: 一种用于延长闪存设备的使用寿命的方法和系统。 闪存器件是动态配置的，以每单元单位（SBC）存储模式或每单元多位（MBC）模式存储数据。 在MBC存储模式中，单元可以具有多种可能状态之一，其中每个状态由相应的阈值电压范围定义。 在SBC模式中，单元可以具有与彼此不相邻的MBC存储模式的状态对应的阈值电压的状态，以改善单元的可靠性特性。

公开(公告)号：US08675425B2

公开(公告)日：2014-03-18

申请号：US13836702

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Roland Schuetz ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

Abstract translation: 存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。 便利减少引脚数接口，将多个选通信号降低到单个选通信号。 此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。 本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

公开(公告)号：US20130201775A1

公开(公告)日：2013-08-08

申请号：US13836702

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Roland Schuetz ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

公开(公告)号：US20130170294A1

公开(公告)日：2013-07-04

申请号：US13777485

申请日：2013-02-26

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  William F. Petrie

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  G11C2211/5646 ,  G11C2211/5647

Abstract: A Multiple-bit per Cell (MBC) non-volatile memory apparatus, method, and system wherein a controller for writing/reading data to/from a memory array controls polarity of data by selectively inverting data words to maximize a number of bits to be programmed within (M-1) virtual pages and selectively inverts data words to minimize a number of bits to be programmed in an Mth virtual page where M is the number of bits per cell. A corresponding polarity control flag is set when a data word is inverted. Data is selectively inverted according the corresponding polarity flag when being read from the M virtual pages. A number of the highest threshold voltage programming states in reduced. This provides tighter distribution of programmed cell threshold voltage, reduced power consumption, reduced programming time, and enhanced device reliability.

Abstract translation: 一种多位单元（MBC）非易失性存储装置，方法和系统，其中用于向/从存储器阵列写入/读取数据的控制器通过选择性地反转数据字来控制数据的极性，以使位的数量最大化 （M-1）个虚拟页面内编程，并选择性地反转数据字以最小化要在第M个虚拟页面中编程的位数，其中M是每个单元的位数。 当数据字反转时，设置相应的极性控制标志。 当从M个虚拟页面读取时，根据相应的极性标志选择性地反转数据。 许多最高阈值电压编程状态在减少。 这提供了编程单元阈值电压的更严格的分配，降低的功耗，减少的编程时间和增强的器件可靠性。