公开(公告)号：US08654601B2

公开(公告)日：2014-02-18

申请号：US13867437

申请日：2013-04-22

Applicant: Mosaid Technologies Incorporated

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract translation: 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US11600323B2

公开(公告)日：2023-03-07

申请号：US17246190

申请日：2021-04-30

Applicant: Mosaid Technologies Incorporated

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G06F1/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/06

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US08879311B2

公开(公告)日：2014-11-04

申请号：US13973600

申请日：2013-08-22

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: G11C11/00 ,  G11C13/00 ,  G11C8/08 ,  G11C8/14

CPC classification number: G11C13/0069 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0071

Abstract: A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby.

Abstract translation: 一种用于改善子字线响应的方法包括生成由至少一个用户参数确定的可变衬底偏置。 可变衬底偏置被施加到存储器的所选子块中的子字线驱动器。 通过修改子字线驱动器的可变衬底偏置来改变子字线驱动器的跨导，从而最小化与子字线驱动器通信的子字线上的电压干扰。

公开(公告)号：US08837655B2

公开(公告)日：2014-09-16

申请号：US13887937

申请日：2013-05-06

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: H04L7/00 ,  G11C7/10 ,  G11C5/02 ,  G11C7/20 ,  G11C7/22 ,  G11C7/02 ,  H01L25/065

CPC classification number: G06F1/10 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H04L7/0008 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller.

Abstract translation: 系统包括存储器控制器和与存储器控制器串联连接的多个存储器件。 系统操作与以源同步时钟结构的方式提供的时钟同步。 源同步时钟结构包括一个PLL（锁相环），其重新形成输入时钟，并提供重构时钟。 PLL提供90°相位的移位时钟。 相移时钟和数据从第一设备发送到第二设备。 时钟相移提供了要传输数据的中心边沿时钟。 设备被分配唯一的ID。 最后一个设备的ID号码的最低有效位用于确定时钟对准：边沿或中心对齐时钟与存储器控制器产生的数据。

公开(公告)号：US08694692B2

公开(公告)日：2014-04-08

申请号：US13671248

申请日：2012-11-07

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC: G06F3/00

CPC classification number: G06F13/4243

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

公开(公告)号：US11948629B2

公开(公告)日：2024-04-02

申请号：US18109390

申请日：2023-02-14

Applicant: Mosaid Technologies Incorporated

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C11/56 ,  G06F1/12 ,  G11C7/10 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/06 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09257193B2

公开(公告)日：2016-02-09

申请号：US14156047

申请日：2014-01-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US08677084B2

公开(公告)日：2014-03-18

申请号：US13655582

申请日：2012-10-19

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: G06F13/00

CPC classification number: G06F3/0664 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/068 ,  G06F9/4408 ,  G06F12/0868 ,  G06F2212/217 ,  Y02D10/13 ,  Y02D10/154

Abstract: A system, method and machine-readable medium are provided to configure a non-volatile memory (NVM) including a plurality of NVM modules, in a system having a hard disk drive (HDD) and an operating system (O/S). In response to a user selection of a hybrid drive mode for the NVM, the plurality of NVM modules are ranked according to speed performance. Boot portions of the O/S are copied to a highly ranked NVM module, or a plurality of highly ranked NVM modules, and the HDD and the highly ranked NVM modules are assigned as a logical hybrid drive of the computer system. Ranking each of the plurality of NVM modules can include carrying out a speed performance test. This approach can provide hybrid disk performance using conventional hardware, or enhance performance of an existing hybrid drive, while taking into account relative performance of available NVM modules.

Abstract translation: 在具有硬盘驱动器（HDD）和操作系统（O / S）的系统中，提供了一种系统，方法和机器可读介质来配置包括多个NVM模块的非易失性存储器（NVM）。 响应于用户选择NVM的混合驱动模式，根据速度性能对多个NVM模块进行排序。 O / S的引导部分被复制到高排名的NVM模块或多个高排名的NVM模块，并且HDD和高排名的NVM模块被分配为计算机系统的逻辑混合驱动器。 对多个NVM模块中的每一个进行排序可以包括进行速度性能测试。 这种方法可以使用常规硬件提供混合磁盘性能，或提高现有混合驱动器的性能，同时考虑可用的NVM模块的相对性能。

公开(公告)号：US20130212304A1

公开(公告)日：2013-08-15

申请号：US13726320

申请日：2012-12-24

Applicant: MOSAID Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: G06F12/06

CPC classification number: G06F12/0669 ,  G06F13/4247

Abstract: A technique for automatically establishing device IDs for devices in a daisy chain cascade arrangement. For each device, a write ID operation is initiated at the device to cause the device to enter a generate/write ID mode. While in this mode, a first value is input to the device. The device generates a second value from the first value. The device outputs the generated second value from the device to a next device in the daisy chain cascade which uses the second value as a first value for the next device. The device then establishes its ID from the first value. The process is repeated for all devices in the daisy chain cascade arrangement.

Abstract translation: 一种用于以菊花链级联布置自动建立设备的设备ID的技术。 对于每个设备，在设备上启动写入ID操作，以使设备进入生成/写入ID模式。 在此模式下，第一个值被输入到设备。 设备从第一个值生成第二个值。 设备将生成的第二值从设备输出到菊花链级联中的下一个设备，其使用第二个值作为下一个设备的第一个值。 然后设备从第一个值建立其ID。 对菊花链级联布置中的所有设备重复该过程。

公开(公告)号：USRE44926E1

公开(公告)日：2014-06-03

申请号：US13774477

申请日：2013-02-22

Applicant: Mosaid Technologies Incorporated

Inventor： Hong Beom Pyeon

IPC: G11C8/00

CPC classification number: G11C7/1051 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1078 ,  G11C16/30

Abstract: Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices.

Abstract translation: 将适配的块隔离方法应用于串行连接的存储器组件可以减轻串联连接的非易失性存储器件中的漏电流的影响。 响应于确定给定存储器组件不是命令的预期目的地，给定存储器组件的多个核心组件可以被置于低功耗模式中，同时将输入/输出组件保持在主动操作模式。 方便地，所公开的系统的方面减少了电流，而不会在存储器件中增加许多逻辑块。