公开(公告)号：US5100818A

公开(公告)日：1992-03-31

申请号：US637423

申请日：1991-01-04

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region. Another part of the control gate is formed on the floating gate through an insulating film. The first impurity region is connected to a bit line and the fourth impurity region is connected to a source region respectively.

公开(公告)号：US5162262A

公开(公告)日：1992-11-10

申请号：US727032

申请日：1991-07-08

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L21/3211 ,  H01L21/76843 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002 ,  Y10S148/019

摘要： An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a secondary refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.

摘要翻译： 根据本发明的半导体器件的互连层具有与难熔金属硅化物层，第一耐火金属氮化物层和第二难熔金属的底部形成的多层结构的导体层的接触部分 氮化物层。 钛或钨用作难熔金属。 通过对耐火金属层进行热氮化而形成第二难熔金属氮化物。 通过热处理形成的第二耐火金属氮化物层具有紧密堆积的晶体结构，并且具有优异的阻挡特性。

公开(公告)号：US5093277A

公开(公告)日：1992-03-03

申请号：US487322

申请日：1990-03-02

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/76227 ,  H01L21/32

摘要： Here is disclosed an improved polysilicon pad LOCOS method. An underlying oxide film is formed on a main surface of a semiconductor substrate. Over the underlying oxide film, polysilicon to be a field oxide film is then deposited. Subsequently, a nitride film is formed on the polysilicon. Thereafter, the nitride film is patterned to leave patterns of a predetermined configuration in an area to be a device region. Using the patterned nitride film as a mask, the polysilicon other than a portion beneath the mask is thermally oxidized to form a field oxide film on the main surface of the semiconductor substrate. The nitride film having served as a mask is then removed to expose the unoxidized polysilicon remaining under the mask. Subsequently, the unoxidized polysilicon is etched away under predetermined conditions which do not allow any etching of the underlying oxide film. According to the present method, it is possible to increase the film thickness of the field oxide film without opening any hole in the surface of the semiconductor substrate. As a result, a highly integrated semiconductor device can be obtained.

摘要翻译： 这里公开了改进的多晶硅焊盘LOCOS方法。 在半导体衬底的主表面上形成下面的氧化膜。 然后在底层氧化物膜上沉积多晶硅作为场氧化物膜。 随后，在多晶硅上形成氮化物膜。 此后，对氮化膜进行图案化，以便在作为器件区域的区域中留下预定结构的图案。 使用图案化的氮化物膜作为掩模，除了掩模下面的部分之外的多晶硅被热氧化以在半导体衬底的主表面上形成场氧化膜。 用作掩模的氮化物膜然后被去除以暴露残留在掩模下面的未氧化的多晶硅。 随后，在不允许对下面的氧化膜进行任何蚀刻的预定条件下，蚀刻掉未氧化的多晶硅。 根据本方法，可以在半导体衬底的表面中没有打开任何孔的情况下增加场氧化膜的膜厚。 结果，可以获得高度集成的半导体器件。

公开(公告)号：US5051948A

公开(公告)日：1991-09-24

申请号：US434692

申请日：1989-10-20

申请人： Kiyoto Watabe ,  Hirofumi Shinohara ,  Takahisa Eimori ,  Hideaki Arima ,  Natsuo Ajika ,  Yuichi Nakashima ,  Shinichi Satoh

发明人： Kiyoto Watabe ,  Hirofumi Shinohara ,  Takahisa Eimori ,  Hideaki Arima ,  Natsuo Ajika ,  Yuichi Nakashima ,  Shinichi Satoh

IPC分类号： G11C15/04

CPC分类号： G11C15/046

摘要： In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.

摘要翻译： PCT No.PCT / JP89 / 00179 Sec。 371日期1989年10月20日第 102（e）日期1989年10月20日PCT提交1989年2月22日PCT公布。 出版物WO89 / 08314 日本1989年9月8日。在根据本发明的内容可寻址存储器（CAM）单元中，一对非易失性存储晶体管保持数据，由此即使切断功率，存储的数据也不会消失。 这些非易失性晶体管的导通端子连接到位线对，从而可以从位线对直接读出所存储的数据。 此外，本发明CAM系统将在匹配线中流动的电流的值转换为电压值以执行内容参考，因此可以将其用作关联存储器系统。

公开(公告)号：US5049975A

公开(公告)日：1991-09-17

申请号：US492032

申请日：1990-03-12

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/3205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/43 ,  H01L29/45

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/3211 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002 ,  Y10S257/915

摘要： An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a second refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.

摘要翻译： 根据本发明的半导体器件的互连层具有与难熔金属硅化物层，第一耐火金属氮化物层和第二难熔金属的底部形成的多层结构的导体层的接触部分 氮化物层。 钛或钨用作难熔金属。 通过对耐火金属层进行热氮化而形成第二难熔金属氮化物。 通过热处理形成的第二耐火金属氮化物层具有紧密堆积的晶体结构，并且具有优异的阻挡特性。

公开(公告)号：US5892702A

公开(公告)日：1999-04-06

申请号：US710901

申请日：1996-09-24

申请人： Tatsuo Okamoto ,  Atsushi Hachisuka ,  Hideaki Arima ,  Mitsuya Kinoshita

发明人： Tatsuo Okamoto ,  Atsushi Hachisuka ,  Hideaki Arima ,  Mitsuya Kinoshita

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： In a semiconductor memory device having cylindrical capacitors, word lines and a bit line are formed on a semiconductor substrate. A cylindrical storage node is connected to a conductive layer. The cylindrical storage node is provided at its inner wall with protruded conductive conductors which protrudes in a radially inward direction of the cylindrical storage node. A surface of the cylindrical storage node is covered with a capacitor insulating film. The outer surface of the cylindrical storage node is covered with a cell plate with the capacitor insulating film therebetween.

摘要翻译： 在具有圆柱形电容器的半导体存储器件中，在半导体衬底上形成字线和位线。 圆柱形存储节点连接到导电层。 圆柱形存储节点在其内壁处设置有突出的导电导体，其在圆柱形存储节点的径向向内的方向上突出。 圆柱形存储节点的表面被电容器绝缘膜覆盖。 圆柱形存储节点的外表面被其间具有电容器绝缘膜的单元板覆盖。

公开(公告)号：US5506164A

公开(公告)日：1996-04-09

申请号：US380181

申请日：1995-01-30

申请人： Mitsuya Kinoshita ,  Tatsuo Okamoto ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Mitsuya Kinoshita ,  Tatsuo Okamoto ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.

摘要翻译： 半导体存储器件包括在其主表面上形成有导电层6的半导体衬底1。 字线4c，4d和位线11形成在半导体衬底上。 提供绝缘膜8,12以覆盖字线4c，4d和位线11.隔离膜14设置在绝缘膜8,12上，用于保护绝缘膜8,12免受蚀刻。 圆柱形存储节点170电连接到导电层6.圆柱形存储节点170包括底部导电部分17a和侧壁导电部分17b。 存储节点170的外表面被电容器绝缘膜112覆盖。圆筒形存储节点170的外表面被电池板22覆盖，电容器绝缘膜112插入其间。

公开(公告)号：US5408114A

公开(公告)日：1995-04-18

申请号：US70521

申请日：1993-06-03

申请人： Mitsuya Kinoshita ,  Tatsuo Okamoto ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Mitsuya Kinoshita ,  Tatsuo Okamoto ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The semiconductor memory device includes a semiconductor substrate 1 having a conductive layer 6 formed on its main surface. Word lines 4c, 4d and a bit line 11 is formed on the semiconductor substrate. Insulating films 8, 12 are provided to cover the word lines 4c, 4d and the bit line 11. A barrier film 14 is provided on the insulating films 8, 12 for protecting the insulating films 8, 12 from etchant. A cylindrical storage node 170 is electrically connected to the conductive layer 6. The cylindrical storage node 170 includes a bottom conductive portion 17a and a sidewall conductive portion 17b. An outer surface of the storage node 170 is covered with a capacitor insulating film 112. The outer surface of the cylindrical storage node 170 is covered with a cell plate 22, with the capacitor insulating film 112 interposed therebetween.

摘要翻译： 半导体存储器件包括在其主表面上形成有导电层6的半导体衬底1。 字线4c，4d和位线11形成在半导体衬底上。 提供绝缘膜8,12以覆盖字线4c，4d和位线11.隔离膜14设置在绝缘膜8,12上，用于保护绝缘膜8,12免受蚀刻。 圆柱形存储节点170电连接到导电层6.圆柱形存储节点170包括底部导电部分17a和侧壁导电部分17b。 存储节点170的外表面被电容器绝缘膜112覆盖。圆筒形存储节点170的外表面被电池板22覆盖，电容器绝缘膜112插入其间。

公开(公告)号：US07782700B2

公开(公告)日：2010-08-24

申请号：US12420275

申请日：2009-04-08

申请人： Kenichi Kuboyama ,  Hideaki Arima

发明人： Kenichi Kuboyama ,  Hideaki Arima

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C29/02 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

摘要： In a semiconductor or memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and the first ODT circuit, and detects a level of a voltage applied to the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.

摘要翻译： 在半导体或存储器件中，在终端电压端口和命令输入端口之间提供第一ODT（On Die Termination）电路。 第一ODT控制电路连接在终端电压端口和第一ODT电路之间，并且检测施加到终端电压端口的电压的电平，并且控制第一ODT电路以连接端接电压端口和命令输入端口，基于 检测结果。

公开(公告)号：US07754562B2

公开(公告)日：2010-07-13

申请号：US12368606

申请日：2009-02-10

申请人： Yoshinori Tanaka ,  Masahiro Shimizu ,  Hideaki Arima

发明人： Yoshinori Tanaka ,  Masahiro Shimizu ,  Hideaki Arima

IPC分类号： H01L21/336

CPC分类号： H01L27/0629 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

摘要： A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance.