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公开(公告)号：US07179700B2
公开(公告)日：2007-02-20
申请号：US10895553
申请日：2004-07-21
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28044 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/456
摘要： An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to the P work function of 5.2 electron volts, and the N-type source/drain contacts of the N channel transistors have a silicide that is close to the N work function of 4.1 electron volts. This provides for a lower resistance at the interface between these source/drain contact regions and the corresponding silicide. These suicides with differing work functions are achieved with implants as needed. For example, for N-type source/drain contacts and a base metal of cobalt, titanium, or nickel, the implanted material is platinum and/or iridium. For the P-type, the implanted material is erbium, yttrium, dysprosium, gadolinium, hafnium, or holmium.
摘要翻译： N沟道晶体管和P沟道晶体管的源极/漏极接触不同的自杀，以提供低电阻触点。 选择硅化物以提供工作功能的良好匹配。 P沟道晶体管的P型源极/漏极触点具有接近5.2电子伏特的P功函数的硅化物，并且N沟道晶体管的N型源极/漏极触点具有接近于 4.1电子伏特的N工作功能。 这提供了在这些源极/漏极接触区域和相应的硅化物之间的界面处的较低电阻。 具有不同工作功能的这些自杀根据需要用植入物实现。 例如，对于N型源极/漏极触点和钴，钛或镍的母体金属，植入的材料是铂和/或铱。 对于P型，植入的材料是铒，钇，镝，钆，铪或钬。
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22.发明授权公开(公告)号：US06987063B2
公开(公告)日：2006-01-17
申请号：US10865452
申请日：2004-06-10
IPC分类号： H01L21/44
CPC分类号： C23C14/0005 , C23C16/4401 , C23C16/56 , H01L21/3141 , H01L21/31604 , H01L21/31645
摘要： A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.
摘要翻译： 通过避免包含降低金属介电常数的污染元素的方法，形成具有高介电常数的含金属的半导体层。 含金属的半导体层形成在室内的基板上。 引入前体以沉积至少一部分含金属的半导体层。 前体含有一种或多种元素，如果允许沉积在含金属的层中，则会成为杂质元素。 反应气体用于通过从由前体引入室中的含金属层去除杂质元素来净化含金属层。
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公开(公告)号：US08404594B2
公开(公告)日：2013-03-26
申请号：US11139765
申请日：2005-05-27
IPC分类号： C23F1/00 , H01L21/461 , H01L21/302 , B44C1/22
CPC分类号： H01L21/0228 , H01L21/02142 , H01L21/02175 , H01L21/265 , H01L21/31111 , H01L21/31116 , H01L21/31122 , H01L21/3141 , H01L21/31645 , H01L21/823462 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.
摘要翻译： 半导体工艺和装置包括通过在第一高k栅极电介质（121）上形成第一栅电极（151）并且形成第二栅极电极（161）至少形成第一栅极电极（151,161） 与第一栅极电介质（121）不同的第二高k栅极电介质（122）。 可以通过沉积和选择性蚀刻高k电介质材料的初始层（例如14）来形成高k栅极电介质层（121,122）之一或两者。 沉积时，初始层（14）具有暴露表面（18）和初始预定晶体结构。 通过改变暴露的薄表面层中的初始晶体结构，准备初始层（14）的暴露的薄表面层（20）用于蚀刻。 暴露的薄表面层中的改性晶体结构可以通过施加选择性蚀刻如HF或HCl来去除。
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24.发明授权Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer 有权用于增强含金属层成核的半导体表面的等离子体处理公开(公告)号：US08030220B2
公开(公告)日：2011-10-04
申请号：US12579072
申请日：2009-10-14
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译： 提供一种形成电介质层的方法。 该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。 该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为 范围为1到60秒。 该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。
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25.发明授权Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer 有权用于增强含金属层成核的半导体表面的等离子体处理公开(公告)号：US07618902B2
公开(公告)日：2009-11-17
申请号：US11290320
申请日：2005-11-30
IPC分类号： H01L21/31 , H01L21/469 , H01L21/336
CPC分类号： H01L21/02315 , H01L21/02052 , H01L21/02142 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/2822 , H01L21/306 , H01L21/3141 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for forming a dielectric layer is provided. The method may include providing a semiconductor surface and etching a thin layer of the semiconductor substrate to expose a surface of the semiconductor surface, wherein the exposed surface is hydrophobic. The method may further include treating the exposed surface of the semiconductor substrate with plasma to neutralize a hydrophobicity associated with the exposed surface, wherein the exposed surface is treated using plasma with a power in a range of 100 watts to 500 watts and for duration in a range of 1 to 60 seconds. The method may further include forming a metal-containing layer on a top surface of the plasma treated surface using an atomic layer deposition process.
摘要翻译： 提供一种形成电介质层的方法。 该方法可以包括提供半导体表面并蚀刻半导体衬底的薄层以暴露半导体表面的表面，其中暴露表面是疏水性的。 该方法可以进一步包括用等离子体处理半导体衬底的暴露表面以中和与暴露表面相关联的疏水性，其中暴露表面使用等离子体处理，功率范围为100瓦至500瓦，并且持续时间为 范围为1到60秒。 该方法可以进一步包括使用原子层沉积工艺在等离子体处理的表面的顶表面上形成含金属层。
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26.发明授权Method for removing metal foot during high-k dielectric/metal gate etching 有权在高k电介质/金属栅极蚀刻期间去除金属脚的方法公开(公告)号：US07579282B2
公开(公告)日：2009-08-25
申请号：US11331786
申请日：2006-01-13
IPC分类号： H01L21/285 , H01L21/3065
CPC分类号： H01L21/02071 , H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L21/32139 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).
摘要翻译： 金属层蚀刻工艺沉积，图案和各向异性地将多晶硅层（24）向下蚀刻到下面的金属层（22）以形成蚀刻的多晶硅结构（54），其上形成有在其侧壁表面上的聚合物层（50,52）。 去除聚合物层（50,52）以暴露金属层（22）的另外的表面区域（60,62），并且在蚀刻的多晶硅结构（54）的侧壁表面上形成介电层（80,82） ）。 接下来，通过同时对电介质层（80,82）充电以改变电介质层附近的等离子体离子轨迹，等离子体蚀刻金属层（22）以形成具有基本上垂直的侧壁表面（97,99）的蚀刻金属层（95） （80,82），使得等离子体离子（92,94）以更垂直的角度冲击侧壁表面（97,99）以增强蚀刻金属层（95）的侧壁表面（97,99）的蚀刻。
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公开(公告)号：US20080254617A1
公开(公告)日：2008-10-16
申请号：US11733519
申请日：2007-04-10
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing process for forming a contact plug includes sequentially depositing a titanium or tantalum contact layer (30), a titanium nitride barrier layer (40), and a tungsten seed layer (50) in a contact opening (24). The contact hole (24) is then filled up from a bottom surface of the contact opening by electroplating a copper layer (60) so that no voids are formed in the contact opening (24). Any excess metal is removed with a CMP process to form the contact plugs (70), where the CMP process may also used to thin or remove one or more of the contact/seed/barrier layers (30, 40, 50).
摘要翻译： 用于形成接触插塞的半导体器件制造方法包括在接触开口（24）中顺序地沉积钛或钽接触层（30），氮化钛阻挡层（40）和钨籽晶层（50）。 接触孔（24）然后通过电镀铜层（60）从接触开口的底表面填充，使得在接触开口（24）中不形成空隙。 通过CMP工艺去除任何多余的金属以形成接触塞（70），其中CMP工艺也可以用于稀释或去除一个或多个接触/种子/阻挡层（30,40,50）。
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公开(公告)号：US07109079B2
公开(公告)日：2006-09-19
申请号：US11043337
申请日：2005-01-26
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823864 , H01L21/823835 , H01L21/823842
摘要： A method for forming a semiconductor device (100) includes a semiconductor substrate (102) having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and forming a capping layer over the oxidation resistant barrier layer. In one embodiment, the conductive metal oxide is IrO2, MoO2, and RuO2, and the oxidation resistant barrier layer includes TiN.
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公开(公告)号：US07001852B2
公开(公告)日：2006-02-21
申请号：US10836149
申请日：2004-04-30
IPC分类号： H01L21/31
CPC分类号： H01L21/02255 , H01L21/02299 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/31645 , H01L29/513
摘要： A method of making a high quality thin dielectric layer includes annealing a substrate and a base oxide layer overlying a top surface of the substrate at a first temperature in a first ambient and annealing the substrate and base oxide layer at a second temperature in a second ambient subsequent to the first anneal. The first ambient includes an inert gas ambient selected from the group consisting of a nitrogen, argon, and helium ambient. Prior to the first anneal, the base oxide layer has an initial thickness and an initial density. The first anneal causes a first density and thickness change in the base oxide layer from the initial thickness and density to a first thickness and density, with no incorporation of nitrogen, argon, or helium of the ambient within the base oxide layer. The first thickness is less than the initial thickness and the first density is greater than the initial density. The second anneal causes a second density and thickness change in the base oxide layer from the first thickness and density to a second thickness and density. The second thickness is larger than the first thickness and the second density is on the order of the greater than or equal to the first density.
摘要翻译： 制造高品质薄介电层的方法包括在第一环境中的第一温度下对衬底和覆盖在衬底的顶表面上的基底氧化物层进行退火，并在第二环境中的第二温度退火衬底和基底氧化物层 在第一退火之后。 第一环境包括选自氮，氩和氦环境的惰性气体环境。 在第一退火之前，基底氧化物层具有初始厚度和初始密度。 第一次退火使基底氧化物层中的初始密度和厚度变化从初始厚度和密度到第一厚度和密度，而不会在基底氧化物层内引入环境的氮，氩或氦。 第一厚度小于初始厚度，第一密度大于初始密度。 第二退火导致基础氧化物层中的第二密度和厚度从第一厚度和密度变化到第二厚度和密度。 第二厚度大于第一厚度，第二密度大于或等于第一密度。
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公开(公告)号：US06933227B2
公开(公告)日：2005-08-23
申请号：US10691984
申请日：2003-10-23
CPC分类号： H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A process for forming a semiconductor structure includes forming a gate dielectric overlying a substrate, a conductive gate electrode overlying the gate dielectric, a barrier layer overlying and in physical contact with the conductive gate electrode, and an organic anti-reflective coating (ARC) layer overlying and in physical contact with the barrier layer.
摘要翻译： 一种用于形成半导体结构的工艺包括形成覆盖在衬底上的栅极电介质，覆盖栅极电介质的导电栅电极，覆盖并与导电栅电极物理接触的阻挡层，以及有机抗反射涂层（ARC）层 覆盖并与屏障层物理接触。
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