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公开(公告)号：US07179700B2
公开(公告)日：2007-02-20
申请号：US10895553
申请日：2004-07-21
IPC分类号： H01L21/8238
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28044 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/456
摘要： An N channel transistor and a P channel transistor have their source/drains contacts with different suicides to provide for low resistance contacts. The silicides are chosen to provide good matching of the work functions. The P-type source/drain contacts of the P channel transistors have a silicide that is close to the P work function of 5.2 electron volts, and the N-type source/drain contacts of the N channel transistors have a silicide that is close to the N work function of 4.1 electron volts. This provides for a lower resistance at the interface between these source/drain contact regions and the corresponding silicide. These suicides with differing work functions are achieved with implants as needed. For example, for N-type source/drain contacts and a base metal of cobalt, titanium, or nickel, the implanted material is platinum and/or iridium. For the P-type, the implanted material is erbium, yttrium, dysprosium, gadolinium, hafnium, or holmium.
摘要翻译： N沟道晶体管和P沟道晶体管的源极/漏极接触不同的自杀，以提供低电阻触点。 选择硅化物以提供工作功能的良好匹配。 P沟道晶体管的P型源极/漏极触点具有接近5.2电子伏特的P功函数的硅化物，并且N沟道晶体管的N型源极/漏极触点具有接近于 4.1电子伏特的N工作功能。 这提供了在这些源极/漏极接触区域和相应的硅化物之间的界面处的较低电阻。 具有不同工作功能的这些自杀根据需要用植入物实现。 例如，对于N型源极/漏极触点和钴，钛或镍的母体金属，植入的材料是铂和/或铱。 对于P型，植入的材料是铒，钇，镝，钆，铪或钬。
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公开(公告)号：US06849487B2
公开(公告)日：2005-02-01
申请号：US10445791
申请日：2003-05-27
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/51 , H01L29/786
CPC分类号： H01L29/785 , B82Y10/00 , H01L21/28035 , H01L21/28123 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28273 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66795 , Y10S438/947
摘要： A method of forming a conductive structure having a length that is less than the length define by photolithographic patterning. A silicon layer (12) is formed in a MeOx dielectric layer (11) is photolithographically patterned to a predetermined first length. A metal layer (31) is formed conformally to at least the sidewalls of the silicon layer and then is reacted with the silicon to form a metal silicide (41). In particular, metal silicide abutments (411,412) are formed contiguous to sidewalls (421,422) of a reduced conductor (42). The remaining metal layer and the metal silicide are etched away, resulting in a conductor having predetermined second length that is less than the predetermined first length.
摘要翻译： 通过光刻图案形成具有小于长度的长度的导电结构的方法。 在MeOx电介质层（11）中形成的硅层（12）被光刻地图案化到预定的第一长度。 金属层（31）至少与硅层的侧壁共形形成，然后与硅反应形成金属硅化物（41）。 特别地，与还原导体（42）的侧壁（421,422）邻接地形成金属硅化物接合部（411,412）。 蚀刻剩余的金属层和金属硅化物，导致具有小于预定第一长度的预定第二长度的导体。
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公开(公告)号：US07288458B2
公开(公告)日：2007-10-30
申请号：US11302770
申请日：2005-12-14
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
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4.发明授权Dual metal gate electrode semiconductor fabrication process and structure thereof 失效双金属栅电极半导体制造工艺及其结构公开(公告)号：US07074664B1
公开(公告)日：2006-07-11
申请号：US11092418
申请日：2005-03-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.
摘要翻译： 半导体制造工艺包括图案化覆盖栅极电介质的第一栅极电极层。 第二栅极电极层形成在第一栅极电极层和栅极电介质上。 去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。 可以形成第三栅极电极层，覆盖第一和第二栅电极层。 第一栅极电极层可以包括TiN并且主要驻留在PMOS区域上，而第二栅极电极层可以包括TaC或TaSiN并且主要覆盖NMOS区域。 去除第二栅极电极层的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层的暴露部分的情况下执行化学机械处理（CMP）。
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5.发明授权公开(公告)号：US07071038B2
公开(公告)日：2006-07-04
申请号：US10946938
申请日：2004-09-22
IPC分类号： H01L21/84
CPC分类号： H01L21/28185 , H01L21/3213 , H01L29/513 , H01L29/517 , Y10S438/977 , Y10S438/981
摘要： A method for forming a semiconductor device (10) creates a dielectric layer (18) with high dielectric constant. An interfacial layer (14) is formed over a semiconductor substrate (12). A dielectric layer (16) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions (24, 26) within the semiconductor substrate.
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公开(公告)号：US07030001B2
公开(公告)日：2006-04-18
申请号：US10827202
申请日：2004-04-19
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , B82Y10/00 , B82Y30/00 , C23C16/042 , H01L21/28079 , H01L29/495 , H01L29/4958 , H01L29/7833
摘要： One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
摘要翻译： 一个实施例在衬底上形成栅极电介质层，然后在其中将形成第一器件类型的栅极电介质层的部分上选择性地沉积第一金属层。 不同于第一金属层的第二金属层形成在将形成第二器件类型的栅极电介质层的暴露部分上。 第一和第二装置类型中的每一种将具有不同的功函数，因为每个将包括与栅极电介质直接接触的不同金属。 在一个实施例中，第一金属层的选择性沉积由ALD执行，并且使用抑制层，其选择性地形成在栅极电介质层上，使得第一金属层可以仅选择性地沉积在栅极的那些部分 未被抑制层覆盖的介电层。
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7.发明授权Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode 有权具有双金属氧化物栅极电介质和单金属栅电极的半导体工艺和集成电路公开(公告)号：US06897095B1
公开(公告)日：2005-05-24
申请号：US10843850
申请日：2004-05-12
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
摘要翻译： 半导体制造工艺包括在第一和第二阱区域分别形成第一和第二晶体管，其中第一晶体管具有第一栅极电介质，而第二晶体管具有不同于第一栅极电介质的第二栅极电介质。 第一晶体管具有第一栅电极，第二晶体管具有第二栅电极。 第一和第二栅电极的组成相同。 第一栅极电介质和第二栅极电介质可以都包括高K电介质，例如氧化铪和氧化铝。 第一和第二栅电极都包括覆盖各个栅极电介质的栅极电极层。 栅电极层优选为TaSiN和TaC。 第一和第二栅电极都可以包括覆盖栅电极层的导电层。 在一个这样的实施例中，导电层可以包括多晶硅和钨。
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公开(公告)号：US06790719B1
公开(公告)日：2004-09-14
申请号：US10410043
申请日：2003-04-09
IPC分类号： H01L21337
CPC分类号： H01L21/823468 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.
摘要翻译： 半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质直接接触的第二金属类型的N沟道栅极堆叠。 通过干蚀刻来蚀刻N沟道栅极堆叠和P沟道栅极堆叠的一部分。 通过湿式蚀刻完成P沟道栅叠层的蚀刻。 湿蚀刻对栅极电介质和第二金属类型是非常选择的，使得N沟道晶体管不会通过完成P沟道栅极堆叠的蚀刻而受到不利影响。
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公开(公告)号：US06686282B1
公开(公告)日：2004-02-03
申请号：US10403967
申请日：2003-03-31
IPC分类号： H01L2144
CPC分类号： H01L21/823842 , H01L21/28079
摘要： Using plating, metal gates for N channel and P channel transistors are formed of different materials to achieve the appropriate work function for these N and P channel transistors. The plating is achieved with a seed layer consistent with the growth of the desired layer. The preferred materials are selected from the platinum metals, which comprise ruthenium, ruthenium oxide, iridium, palladium, platinum, nickel, osmium, and cobalt. These are attractive metals because they are relatively high conductivity, can be plated, and provide a good choice of work functions for forming P and N channel transistors.
摘要翻译： 使用电镀，N沟道和P沟道晶体管的金属栅极由不同的材料形成，以实现这些N和P沟道晶体管的适当的功函数。 用与期望层的生长一致的种子层实现电镀。 优选的材料选自包含钌，氧化钌，铱，钯，铂，镍，锇和钴的铂金属。 这些是有吸引力的金属，因为它们具有相对高的导电性，可以被电镀，并且提供了用于形成P和N沟道晶体管的工作功能的良好选择。
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10.发明授权Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same 失效防止两个相邻触点之间的空隙引起的短路的装置和具有该触点的装置的方法公开(公告)号：US06369430B1
公开(公告)日：2002-04-09
申请号：US09823310
申请日：2001-04-02
IPC分类号： H01L2976
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/7682 , H01L21/76897 , H01L21/823425 , H01L21/823475
摘要： Insulating layers between transistors that are very close together may have voids. When contacts are formed in these areas between these close transistors, the contact hole is formed at the void location. These voids may extend between the contact locations that are close together so that the deposition of the conductive material into these contact holes may extend sufficiently into the void to short two such contacts. This is prevented by placing a liner in the contact hole, which constricts the void size in the contact hole, prior to depositing the conductive material. This restricts ingress of conductive material into the void. This prevents the void from being an unwanted conduction path between two contacts that are in close proximity. The bottoms of the contact holes are etched to remove the liner prior to depositing the conductive material.
摘要翻译： 非常靠近在一起的晶体管之间的绝缘层可能具有空隙。 当在这些紧密晶体管之间的这些区域中形成接触时，在空隙位置处形成接触孔。 这些空隙可以在靠近在一起的接触位置之间延伸，使得导电材料沉积到这些接触孔中可以充分地延伸到空隙中以短两个这样的接触。 在沉积导电材料之前，通过将衬垫放置在接触孔中来限制接触孔中的空隙尺寸来防止这种情况。 这限制了导电材料进入空隙。 这样可以防止这两个触点之间的不必要的导电路径的空隙处于非常接近的位置。 在沉积导电材料之前蚀刻接触孔的底部以去除衬垫。
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