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    Method of making a high quality thin dielectric layer
    1.
    发明授权
    Method of making a high quality thin dielectric layer 有权
    制造高品质薄介电层的方法

    公开(公告)号：US07001852B2

    公开(公告)日：2006-02-21

    申请号：US10836149

    申请日：2004-04-30

    申请人： Tien-Ying Luo ,  Olubunmi O. Adetutu ,  Hsing-Huang Tseng

    发明人： Tien-Ying Luo ,  Olubunmi O. Adetutu ,  Hsing-Huang Tseng

    IPC分类号： H01L21/31

    CPC分类号： H01L21/02255 ,  H01L21/02299 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/513

    摘要： A method of making a high quality thin dielectric layer includes annealing a substrate and a base oxide layer overlying a top surface of the substrate at a first temperature in a first ambient and annealing the substrate and base oxide layer at a second temperature in a second ambient subsequent to the first anneal. The first ambient includes an inert gas ambient selected from the group consisting of a nitrogen, argon, and helium ambient. Prior to the first anneal, the base oxide layer has an initial thickness and an initial density. The first anneal causes a first density and thickness change in the base oxide layer from the initial thickness and density to a first thickness and density, with no incorporation of nitrogen, argon, or helium of the ambient within the base oxide layer. The first thickness is less than the initial thickness and the first density is greater than the initial density. The second anneal causes a second density and thickness change in the base oxide layer from the first thickness and density to a second thickness and density. The second thickness is larger than the first thickness and the second density is on the order of the greater than or equal to the first density.

    摘要翻译： 制造高品质薄介电层的方法包括在第一环境中的第一温度下对衬底和覆盖在衬底的顶表面上的基底氧化物层进行退火，并在第二环境中的第二温度退火衬底和基底氧化物层 在第一退火之后。 第一环境包括选自氮，氩和氦环境的惰性气体环境。 在第一退火之前，基底氧化物层具有初始厚度和初始密度。 第一次退火使基底氧化物层中的初始密度和厚度变化从初始厚度和密度到第一厚度和密度，而不会在基底氧化物层内引入环境的氮，氩或氦。 第一厚度小于初始厚度，第一密度大于初始密度。 第二退火导致基础氧化物层中的第二密度和厚度从第一厚度和密度变化到第二厚度和密度。 第二厚度大于第一厚度，第二密度大于或等于第一密度。

    METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA
    2.
    发明申请
    METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA 有权
    通过现场等离子体形成栅极电介质的方法

    公开(公告)号：US20100081290A1

    公开(公告)日：2010-04-01

    申请号：US12241139

    申请日：2008-09-30

    申请人： Tien Ying Luo ,  Olubunmi O. Adetutu

    发明人： Tien Ying Luo ,  Olubunmi O. Adetutu

    IPC分类号： H01L21/285

    CPC分类号： H01L21/31645 ,  C23C16/40 ,  C23C16/402 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45536 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31641 ,  H01L29/517

    摘要： A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

    摘要翻译： 一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层 使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。 在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

    Method of forming a gate dielectric by in-situ plasma
    5.
    发明授权
    Method of forming a gate dielectric by in-situ plasma 有权
    通过原位等离子体形成栅极电介质的方法

    公开(公告)号：US07981808B2

    公开(公告)日：2011-07-19

    申请号：US12241139

    申请日：2008-09-30

    申请人： Tien Ying Luo ,  Olubunmi O. Adetutu

    发明人： Tien Ying Luo ,  Olubunmi O. Adetutu

    IPC分类号： H01L21/3205 ,  H01L21/31 ,  H01L21/336

    CPC分类号： H01L21/31645 ,  C23C16/40 ,  C23C16/402 ,  C23C16/405 ,  C23C16/452 ,  C23C16/45536 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/31641 ,  H01L29/517

    摘要： A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.

    摘要翻译： 一种形成栅极电介质层的方法包括：使用第一等离子体在半导体衬底上形成第一电介质层，执行第一介电层的第一原位等离子体氮化，形成第一氮化电介质层，形成第二电介质层 使用第二等离子体的第一电介质层，执行第二介电层的第二原位等离子体氮化以形成第二氮化介电层; 以及对所述第一氮化介电层和所述第二氮化介电层进行退火，其中所述栅介质层包括所述第一氮化介电层和所述第二氮化介电层。 在其他实施例中，重复使用等离子体形成电介质层并执行原位等离子体氮化的步骤，以形成多于两个的氮化电介质层并用作栅极电介质层。

    SOI active layer with different surface orientation
    9.
    发明授权
    SOI active layer with different surface orientation 有权

    公开(公告)号：US07288458B2

    公开(公告)日：2007-10-30

    申请号：US11302770

    申请日：2005-12-14

    申请人： Olubunmi O. Adetutu ,  Robert E. Jones ,  Ted R. White

    发明人： Olubunmi O. Adetutu ,  Robert E. Jones ,  Ted R. White

    IPC分类号： H01L21/331 ,  H01L21/8222

    CPC分类号： H01L21/76254 ,  H01L21/02002

    摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures having a first surface orientation are formed on a donor wafer. Semiconductor structures having a second surface orientation are formed on a second wafer. Receptor openings are formed on the second wafer. The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.

    Dual metal gate electrode semiconductor fabrication process and structure thereof
    10.
    发明授权
    Dual metal gate electrode semiconductor fabrication process and structure thereof 失效
    双金属栅电极半导体制造工艺及其结构

    公开(公告)号：US07074664B1

    公开(公告)日：2006-07-11

    申请号：US11092418

    申请日：2005-03-29

    申请人： Ted R. White ,  Olubunmi O. Adetutu ,  Robert E. Jones

    发明人： Ted R. White ,  Olubunmi O. Adetutu ,  Robert E. Jones

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842

    摘要： A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.

    摘要翻译： 半导体制造工艺包括图案化覆盖栅极电介质的第一栅极电极层。 第二栅极电极层形成在第一栅极电极层和栅极电介质上。 去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。 可以形成第三栅极电极层，覆盖第一和第二栅电极层。 第一栅极电极层可以包括TiN并且主要驻留在PMOS区域上，而第二栅极电极层可以包括TaC或TaSiN并且主要覆盖NMOS区域。 去除第二栅极电极层的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层的暴露部分的情况下执行化学机械处理（CMP）。