公开(公告)号：US06004862A

公开(公告)日：1999-12-21

申请号：US8320

申请日：1998-01-20

申请人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

发明人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.

摘要翻译： 一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层 具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。

公开(公告)号：US20080142875A1

公开(公告)日：2008-06-19

申请号：US11639666

申请日：2006-12-15

申请人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

发明人： Chungho Lee ,  Wei Zheng ,  Chi Chang ,  Unsoon Kim ,  Hiroyuki Kinoshita

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/1037 ,  H01L29/1083 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66537 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.

摘要翻译： 公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。 所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。 此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件 第二元件的侧壁。 形成与第一存储元件和第二存储元件接触的字线。

公开(公告)号：US20080064165A1

公开(公告)日：2008-03-13

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US07294573B1

公开(公告)日：2007-11-13

申请号：US11035188

申请日：2005-01-13

申请人： Krishnashree Achuthan ,  Unsoon Kim ,  Kashmir Sahota ,  Patriz C. Regalado

发明人： Krishnashree Achuthan ,  Unsoon Kim ,  Kashmir Sahota ,  Patriz C. Regalado

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/7684

摘要： According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

摘要翻译： 根据一个示例性实施例，一种方法包括将位于衬底上的场氧化物区域上的多晶硅层平坦化以形成多晶硅段，其中多晶硅段具有与场氧化物区域的顶表面基本上平面的顶表面， 场氧化物区域具有第一高度，并且多晶硅段具有第一厚度。 该方法还包括在衬底的周边区域上去除硬掩模。 根据该示例性实施例，该方法还包括蚀刻多晶硅段以使多晶硅段具有第二厚度，这导致多晶硅段的顶表面位于场氧化物区的顶表面之下。 可以通过使用湿蚀刻工艺来蚀刻多晶硅段。 多晶硅段位于衬底的芯区域中。

公开(公告)号：US07078314B1

公开(公告)日：2006-07-18

申请号：US10407999

申请日：2003-04-03

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention discloses a memory device having an improved periphery isolation region and core isolation region. A first trench is formed in a core region. Substrate material bordering the first trench is then oxidized to form a first liner. The first liner is then removed. A second trench is then formed in a periphery region. A second oxidation is then performed such that a second liner is formed from the substrate material bordering the first and second trenches. A dielectric trench fill having substantially uniform density is then deposited in the first and second trenches.

摘要翻译： 本发明公开了一种具有改进的外围隔离区域和核心隔离区域的存储器件。 第一沟槽形成在芯区域中。 然后与第一沟槽接壤的衬底材料被氧化以形成第一衬里。 然后将第一个衬垫取出。 然后在周边区域中形成第二沟槽。 然后执行第二氧化，使得第二衬垫由与第一和第二沟槽接壤的衬底材料形成。 然后在第一和第二沟槽中沉积具有基本均匀密度的电介质沟槽填料。

公开(公告)号：US06670691B1

公开(公告)日：2003-12-30

申请号：US10174550

申请日：2002-06-18

申请人： Harpreet K. Sachar ,  Unsoon Kim ,  Jack F. Thomas

发明人： Harpreet K. Sachar ,  Unsoon Kim ,  Jack F. Thomas

IPC分类号： H01L2900

CPC分类号： H01L21/76229

摘要： A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

摘要翻译： 公开了一种用于在半导体制造工艺期间填充窄隔离沟槽的方法。 半导体包括形成在基板的芯区域中的高纵横比窄隔离沟槽和形成在基板的电路区域中的宽隔离沟槽。 在沟槽形成之后，在其中生长热氧化层的厚度足以完全填充高纵横比窄隔离沟槽的所有隔离沟槽中进行厚衬层氧化。 在衬里氧化之后，宽隔离沟槽填充有隔离电介质，由此所有沟槽均匀地填充有最小的空隙。

公开(公告)号：US06664191B1

公开(公告)日：2003-12-16

申请号：US09973131

申请日：2001-10-09

申请人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

发明人： Unsoon Kim ,  Yider Wu ,  Yu Sun ,  Michael K. Templeton ,  Angela T. Hui ,  Chi Chang

IPC分类号： H01L21302

CPC分类号： H01L27/11526 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76229 ,  H01L21/76838 ,  H01L27/11531 ,  Y10S438/975

摘要： A method is provided of forming lines with spaces between memory cells below a minimum printing dimension of a photolithographic tool set. In one aspect of the invention, lines and spaces are formed in a first polysilicon layer that forms floating gates of flash memory cells. STI regions are formed between adjacent memory cells in a substrate to isolate the cells from one another. The first polysilicon layer is deposited over the substrate covering the STI regions. The first polysilicon layer is then planarized by a CMP process or the like to eliminate overlay issues associated with the STI regions. A hard mask layer is deposited over the first polysilicon layer and a first space dimension d1 etched between adjacent memory cells. A conformal nitride layer is deposited over the hard mask layer and an etch step performed to form nitride side walls adjacent the spaces. The nitride side walls reduce the first space dimension to a second space dimension d2, so that spaces can be formed in the first polysilicon layer at a dimension smaller than the minimum printable dimension of the photolithographic tool set.

摘要翻译： 提供了一种在光刻工具组的最小打印尺寸之下形成具有在存储器单元之间的空间的线的方法。 在本发明的一个方面，线和间隔形成在形成闪存单元的浮动栅极的第一多晶硅层中。 STI区域形成在衬底中的相邻存储单元之间，以隔离细胞。 第一多晶硅层沉积在覆盖STI区域的衬底上。 然后通过CMP工艺等将第一多晶硅层平坦化，以消除与STI区域相关联的覆盖问题。 在第一多晶硅层上沉积硬掩模层，并在相邻的存储单元之间蚀刻第一空间尺寸d1。 在硬掩模层上沉积共形氮化物层，并且执行蚀刻步骤以形成邻近空间的氮化物侧壁。 氮化物侧壁将第一空间尺寸减小到第二空间尺寸d2，使得可以以小于光刻工具组的最小可打印尺寸的尺寸在第一多晶硅层中形成空间。

公开(公告)号：US06555867B1

公开(公告)日：2003-04-29

申请号：US08991448

申请日：1997-12-16

申请人： Unsoon Kim

发明人： Unsoon Kim

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L29/4925

摘要： A method for improving the gate coupling in a flash memory core includes forming floating gates of memory element stacks by depositing a first polysilicon layer having relatively small grain size on a tunnel oxide layer and then depositing a second polysilicon layer on the first, the second polysilicon layer being made of relatively large hemispherical-grained (HSG) polysilicon crystals, which improves gate coupling. In contrast, owing to the relatively small size of its grains, the first layer of polysilicon advantageously establishes a relatively flat surface interface with the tunnel oxide layer that is between the memory stacks and the underlying silicon substrate. Conventional control gates are then established above the HSG layer.

摘要翻译： 一种用于改善闪速存储器芯中的栅极耦合的方法包括：通过在隧道氧化物层上沉积具有相对较小晶粒尺寸的第一多晶硅层，然后在第一多晶硅层上沉积第二多晶硅层，形成存储元件堆叠的浮置栅极 层由相对大的半球形（HSG）多晶硅晶体制成，这改善了栅极耦合。 相反，由于其晶粒的尺寸相对较小，所以第一层多晶硅有利地建立了与存储堆和底层硅衬底之间的隧道氧化物层相对平坦的表面界面。 然后在HSG层之上建立传统的控制门。

公开(公告)号：US5981341A

公开(公告)日：1999-11-09

申请号：US986160

申请日：1997-12-05

申请人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun ,  Angela T. Hui

发明人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun ,  Angela T. Hui

IPC分类号： H01L21/762 ,  H01L21/8247 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/76224

摘要： A method for making a self-aligned isolated flash memory core without damaging tunnel oxide layers between memory element stacks and the silicon substrate supporting the stacks includes depositing three sidewall layers on the stacks, prior to etching isolation trenches between the stacks, to thereby shield the tunnel oxide during isolation trench etching.

摘要翻译： 用于制造自对准隔离闪存芯的方法，而不损坏存储元件堆叠和支撑堆叠的硅衬底之间的隧道氧化物层，包括在蚀刻堆叠之间的隔离沟槽之前在堆叠上沉积三个侧壁层，从而屏蔽 隔离沟槽蚀刻期间的隧道氧化物。

公开(公告)号：US08076712B2

公开(公告)日：2011-12-13

申请号：US12840165

申请日：2010-07-20

申请人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

发明人： Chungho Lee ,  Ashot Melik-Martirosian ,  Wei Zheng ,  Timothy Thurgate ,  Chi Chang ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Unsoon Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/42332 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7887 ,  H01L29/7923

摘要： A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

摘要翻译： 提供了双电荷存储节点存储器件及其制造方法。 在一个实施例中，形成包括凹入半导体衬底的第一部分和在衬底上延伸的第二部分的电介质插塞。 在第二部分上形成一层半导体材料。 第一层状结构形成在电介质塞的第二部分的第一侧上，并且第二层结构形成在第二侧上，每个层叠结构覆盖在半导体材料层上，并且包括第一和第二层之间的电荷存储层 和第二电介质层。 将离子注入到衬底中以形成第一位线和第二位线，并且沉积和图案化导电材料层以形成覆盖在电介质插塞和第一和第二分层结构上的控制栅极。