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    Semiconductor device and manufacturing method thereof
    21.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US07588961B2

    公开(公告)日：2009-09-15

    申请号：US11377909

    申请日：2006-03-16

    申请人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

    发明人： Yoshio Shimoida ,  Masakatsu Hoshi ,  Tetsuya Hayashi ,  Hideaki Tanaka ,  Shigeharu Yamagami

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78 ,  H01L21/047 ,  H01L29/1608 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/772 ,  H01L29/7828

    摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.

    摘要翻译： 通常，本公开描述了在反向偏置状态下呈现增加的电阻和减小的漏电流的半导体器件，以及用于制造这种半导体器件的方法。 例如，在一个实施例中，通过在形成在N型外延层上的多晶硅层中引入P +或P-型杂质来获得反向偏置状态下的增加的电阻。 此外，半导体器件在正向偏置状态下保持低电阻。 为了使正向偏置电阻低，在栅电极附近的多晶硅层可以是N +型。 此外，在多晶硅层的表面上形成N +型源极提取区域，以将源电极连接到漏电极，并且当正向偏置时保持低电阻。

    Semiconductor device and method of producing the same
    24.
    发明申请
    Semiconductor device and method of producing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20070210330A1

    公开(公告)日：2007-09-13

    申请号：US11714214

    申请日：2007-03-06

    申请人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

    发明人： Tetsuya Hayashi ,  Masakatsu Hoshi ,  Yoshio Shimoida ,  Hideaki Tanaka ,  Shigeharu Yamagami

    IPC分类号： H01L29/732 ,  H01L21/8234

    CPC分类号： H01L29/267 ,  H01L21/0475 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7828

    摘要： A semiconductor device, includes: a first conductivity type semiconductor base having a main face; a hetero semiconductor region contacting the main face of the semiconductor base and forming a hetero junction in combination with the semiconductor base, the semiconductor base and the hetero semiconductor region in combination defining a junction end part; a gate insulating film defining a junction face in contact with the semiconductor base and having a thickness; and a gate electrode disposed adjacent to the junction end part via the gate insulating film and defining a shortest point in a position away from the junction end part by a shortest interval, a line extending from the shortest point to a contact point vertically relative to the junction face, forming such a distance between the contact point and the junction end part as to be smaller than the thickness of the gate insulating film contacting the semiconductor base.

    摘要翻译： 一种半导体器件，包括：具有主面的第一导电型半导体基底; 与半导体基板的主面接触并与半导体基底结合形成异质结的异质半导体区域，半导体基底和异质半导体区域组合形成连接端部; 限定与半导体基底接触并具有厚度的接合面的栅极绝缘膜; 以及栅电极，其经由所述栅极绝缘膜与所述接合端部相邻设置，并且在远离所述接合端部的位置中以最短间隔限定最短点，从所述最短点到接触点相对于所述接合端垂直延伸的线 接合面在接触点和接合端部之间形成的距离小于与半导体基底接触的栅极绝缘膜的厚度。

    Wide bandgap semiconductor device and method for manufacturing the same
    25.
    发明授权
    Wide bandgap semiconductor device and method for manufacturing the same 有权
    宽带隙半导体器件及其制造方法

    公开(公告)号：US06737677B2

    公开(公告)日：2004-05-18

    申请号：US10410188

    申请日：2003-04-10

    申请人： Yoshio Shimoida ,  Saichirou Kaneko ,  Hideaki Tanaka ,  Masakatsu Hoshi

    发明人： Yoshio Shimoida ,  Saichirou Kaneko ,  Hideaki Tanaka ,  Masakatsu Hoshi

    IPC分类号： H01L310312

    CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L21/049 ,  H01L21/8213 ,  H01L27/0605

    摘要： The present invention provides a wide bandgap semiconductor device encompassing: (a) a drift layer of a first conductivity type made of a wide bandgap semiconductor material; (b) a body region of a second conductivity type made of the wide bandgap semiconductor material, disposed at the top surface of and in the drift layer; (c) a source region of the first conductivity type disposed in the body region; (d) a channel layer of the first conductivity type, disposed in the body region neighboring to the source region and further disposed in the drift layer; and (e) a gate electrode including semiconductor layer at the bottom so that the semiconductor layer directly contact with the top surface of the channel layer, the semiconductor layer made of a semiconductor material having a different bandgap energy from that of the wide bandgap semiconductor material.

    摘要翻译： 本发明提供一种宽带隙半导体器件，其包括：（a）由宽带隙半导体材料制成的第一导电类型的漂移层; （b）由宽带隙半导体材料制成的第二导电类型的体区，设置在漂移层的顶表面上; （c）设置在身体区域中的第一导电类型的源极区域; （d）第一导电类型的沟道层，设置在与源极区相邻的体区中，并且还设置在漂移层中; 和（e）在底部包括半导体层的栅电极，使得半导体层与沟道层的顶表面直接接触，由具有与宽带隙半导体材料的能隙不同的带隙能量的半导体材料制成的半导体层 。

    Device for controlling assembled battery
    27.
    发明授权
    Device for controlling assembled battery 有权
    控制组合电池的装置

    公开(公告)号：US09490646B2

    公开(公告)日：2016-11-08

    申请号：US13885134

    申请日：2010-12-09

    申请人： Tomoya Kubota ,  Yasuhito Miyazaki ,  Yukinari Kato ,  Yoshio Shimoida

    发明人： Tomoya Kubota ,  Yasuhito Miyazaki ,  Yukinari Kato ,  Yoshio Shimoida

    IPC分类号： H02J7/00 ,  G01N27/416 ,  H01M10/42 ,  G01R31/36

    CPC分类号： H02J7/007 ,  G01R31/362 ,  G01R31/3658 ,  G01R31/3679 ,  H01M10/4207 ,  H02J7/0016 ,  Y02T10/7055

    摘要： In a device for controlling an assembled battery provided with a plurality of single batteries, the device includes a capacity adjustment section for adjusting a capacity such that voltages of the single batteries are equalized at a targeted voltage, an internal state detection section for detecting terminal voltages or SOC of the single batteries and for detecting, based on the detected terminal voltages/SOC, a voltage/SOC difference among the single batteries as voltage-difference/SOC-difference data, and a time-series data storage for storing the voltage-difference/SOC-difference data in time-series. Also provided is a prediction section for more appropriately predicting time when the assembled battery becomes an abnormal state, based on a time-dependent change in the voltage-difference/SOC-difference data detected in a voltage/SOC region different from the targeted voltage by a predetermined voltage, among the stored time-series voltage-difference/SOC-difference data.

    摘要翻译： 在一种用于控制设置有多个单电池的组电池的装置中，该装置包括：容量调节部，用于调节单电池的电压在目标电压下均衡的容量;内部状态检测部，用于检测端子电压 或SOC，并且基于检测到的端子电压/ SOC，检测作为电压差/ SOC差数据的单个电池之间的电压/ SOC差，以及用于存储电压 - 差异/ SOC差异数据在时间序列。 还提供了一种预测部分，用于基于在与目标电压不同的电压/ SOC区域中检测到的电压差/ SOC差异数据的时间依赖性变化，更有效地预测组电池变为异常状态时的时间， 存储的时间序列电压差/ SOC差分数据中的预定电压。

    Battery
    28.
    发明授权
    Battery 有权
    电池

    公开(公告)号：US08974954B2

    公开(公告)日：2015-03-10

    申请号：US13392949

    申请日：2010-07-23

    申请人： Yasuhito Miyazaki ,  Takuya Kinoshita ,  Takaaki Abe ,  Yoshio Shimoida

    发明人： Yasuhito Miyazaki ,  Takuya Kinoshita ,  Takaaki Abe ,  Yoshio Shimoida

    IPC分类号： H01M2/06 ,  H01M2/26 ,  H01M2/22 ,  H01M10/0525 ,  H01M10/0585

    CPC分类号： H01M2/26 ,  H01M2/22 ,  H01M2/30 ,  H01M10/0413 ,  H01M10/0525 ,  H01M10/0585

    摘要： Disclosed is a battery having an improved life. Specifically disclosed is a battery which comprises an electric power generating element in which one or more unit cell layers are stacked, each being constituted by sequentially laminating or stacking a positive electrode, an electrolyte and a negative electrode; a first collector plate which is provided on the outermost positive electrode surface of the electric power generating element; a second collector plate which is provided on the outermost negative electrode surface of the electric power generating element; a convex or protruding portion provided on the first collector plate and/or the second collector plate with a width that is not less than a half of the width of the end edge of the collector plate; and a terminal which is attached to the convex portion for retrieving electric current from the convex portion.

    摘要翻译： 公开了具有改善寿命的电池。 具体公开了一种电池，其包括其中堆叠一个或多个单元电池层的发电元件，其分别通过顺序层叠或堆叠正电极，电解质和负电极而构成; 设置在所述发电元件的最外侧正极面上的第一集电板; 设置在所述发电元件的最外侧负极面上的第二集电板; 设置在所述第一集电板和/或所述第二集电板上的凸部或突出部的宽度不小于所述集电板的端缘宽度的一半的宽度; 以及附接到凸部以从凸部取回电流的端子。

    Cell for reducing short circuit and battery incorporating the cell
    30.
    发明授权
    Cell for reducing short circuit and battery incorporating the cell 有权
    用于减少短路的电池和并入电池的电池

    公开(公告)号：US08663832B2

    公开(公告)日：2014-03-04

    申请号：US12190133

    申请日：2008-08-12

    申请人： Takaaki Abe ,  Kazuki Miyatake ,  Osamu Shimamura ,  Masakazu Kobayashi ,  Hideaki Horie ,  Kyoichi Watanabe ,  Yoshio Shimoida

    发明人： Takaaki Abe ,  Kazuki Miyatake ,  Osamu Shimamura ,  Masakazu Kobayashi ,  Hideaki Horie ,  Kyoichi Watanabe ,  Yoshio Shimoida

    IPC分类号： H01M2/14 ,  H01M2/16 ,  H01M2/18

    CPC分类号： H01M4/661 ,  H01M2/26 ,  H01M2/34 ,  H01M10/052 ,  H01M10/4235

    摘要： Disclosed is a cell with a power-generating element and an outer package. The power-generating element includes a unit cell layer including a first electrode, a second electrode and an electrolyte layer disposed between the first and second electrodes. In the first electrode, a first collector is provided with one of a positive electrode active material layer and a negative electrode active material layer. In the second electrode, a second collector is provided with the other one of the positive and negative electrode active material layers. The first and second collectors have thicknesses such that when a conductor from outside penetrates at least two cells and a short circuit is formed between two cells via the conductor, shorted portions of the first and second collectors are fused by the heat generated by the current before the temperature of the cells reaches a predetermined value so that the short circuit is blocked.

    摘要翻译： 公开了具有发电元件和外包装的电池。 发电元件包括​​单元电池层，其包括设置在第一和第二电极之间的第一电极，第二电极和电解质层。 在第一电极中，第一集电体设置有正极活性物质层和负极活性物质层之一。 在第二电极中，第二集电体设置有正极活性物质层和负极活性物质层中的另一个。 第一和第二集电体具有这样的厚度，使得当来自外部的导体穿过至少两个电池并且经由导体在两个电池之间形成短路时，第一和第二集电器的短路部分被由电流产生的热量熔化 电池的温度达到预定值，使得短路被阻塞。