公开(公告)号：US08946821B2

公开(公告)日：2015-02-03

申请号：US13348142

申请日：2012-01-11

申请人： Matthias Goldbach ,  Peter Baars

发明人： Matthias Goldbach ,  Peter Baars

IPC分类号： H01L27/12 ,  H01L27/11 ,  H01L27/02

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

摘要翻译： 提供SRAM集成电路，其具有在硅衬底中及其上制造的SRAM单元的上拉和下拉晶体管。 一层绝缘材料覆盖上拉和下拉晶体管。 SRAM单元的栅极晶体管制造在覆盖绝缘材料层的半导体层中。

公开(公告)号：US20130175627A1

公开(公告)日：2013-07-11

申请号：US13348142

申请日：2012-01-11

申请人： Matthias Goldbach ,  Peter Baars

发明人： Matthias Goldbach ,  Peter Baars

IPC分类号： H01L27/12 ,  H01L21/768

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： SRAM integrated circuits are provided having pull up and pull down transistors of an SRAM cell fabricated in and on a silicon substrate. A layer of insulating material overlies the pull up and pull down transistors. Pass gate transistors of the SRAM cell are fabricated in a semiconducting layer overlying the layer of insulating material.

摘要翻译： 提供SRAM集成电路，其具有在硅衬底中及其上制造的SRAM单元的上拉和下拉晶体管。 一层绝缘材料覆盖上拉和下拉晶体管。 SRAM单元的栅极晶体管制造在覆盖绝缘材料层的半导体层中。

公开(公告)号：US20100078711A1

公开(公告)日：2010-04-01

申请号：US12242039

申请日：2008-09-30

申请人： Matthias Goldbach ,  Jessica Hartwich ,  Lars Dreeskornfeld ,  Arnd Scholz ,  Tobias Mono

发明人： Matthias Goldbach ,  Jessica Hartwich ,  Lars Dreeskornfeld ,  Arnd Scholz ,  Tobias Mono

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

摘要翻译： 一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。 一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。 薄片凹进。 翅片由薄片的中心部分形成。 翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。 形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。 栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

公开(公告)号：US20080296680A1

公开(公告)日：2008-12-04

申请号：US11755137

申请日：2007-05-30

申请人： Matthias Goldbach ,  Stefan Jakschik

发明人： Matthias Goldbach ,  Stefan Jakschik

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L21/823437 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

摘要： A method of making an integrated circuit including doping a fin is disclosed. The method includes providing a substrate having at least one fin of a semiconductor material and carrying out a gas-phase doping of the at least one fin.

摘要翻译： 公开了一种制造包括掺杂鳍片的集成电路的方法。 该方法包括提供具有半导体材料的至少一个翅片并执行至少一个翅片的气相掺杂的基底。

公开(公告)号：US07374992B2

公开(公告)日：2008-05-20

申请号：US11443602

申请日：2006-05-31

申请人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

发明人： Peter Baars ,  Klaus Muemmler ,  Matthias Goldbach

IPC分类号： H01L21/8234

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10811 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.

摘要翻译： 本发明提供了一种用于集成半导体结构的制造方法，包括以下步骤：提供在存储单元区域中具有多个栅极堆叠的半导体衬底和在外围器件区域中的至少一个栅极堆叠; 在所述存储单元区域中的所述多个栅极堆叠上并在所述外围设备区域中的所述至少一个栅极堆叠上形成由一层或多层盖材料构成的盖; 在所述存储单元区域中的两个相邻栅极堆叠之间形成第一接触孔; 在所述存储单元区域和外围设备区域上沉积第一保护层; 将所述至少一个栅极堆叠的所述盖暴露在所述外围设备区域中; 在处理步骤中修改所述外围设备区域中的所述至少一个栅极堆叠的所述暴露的盖，其中所述第一保护层用作所述存储单元区域中的掩模; 在所述外围设备区域中的所述修改的盖上形成第二保护层; 部分地去除所述第一和第二保护层，以便使所述第一和第二保护层大致相同的上层; 从所述第一接触孔去除所述第一保护层; 在所述外围设备区域中形成至少另一个接触孔，所述至少另一个接触孔暴露位于所述外围设备区域中与所述栅极堆叠相邻或所述栅极叠层中的另一个接触区域; 以及用相应的接触插塞填充所述接触孔和所述至少另一个接触孔。

公开(公告)号：US07344953B2

公开(公告)日：2008-03-18

申请号：US11042326

申请日：2005-01-26

申请人： Thomas Hecht ,  Matthias Goldbach ,  Uwe Schröder

发明人： Thomas Hecht ,  Matthias Goldbach ,  Uwe Schröder

IPC分类号： H01L21/20

CPC分类号： C23C16/045 ,  C23C16/45525 ,  H01L21/3065 ,  H01L21/3141 ,  H01L27/10808 ,  H01L27/10829 ,  H01L27/10852 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate surface. The covering layer is patterned in a direction which is vertical with respect to the substrate surface by limiting a process quantity of at least one precursor material and/or by temporarily limiting the deposition process, and is formed as a functional layer or mask for subsequent process steps.

摘要翻译： 在通常为半导体晶片的衬底（其形式为浮雕形式的衬底表面）上，使用沉积工艺来提供在相对于衬底表面垂直或倾斜的工艺表面上的覆盖层 。 通过限制至少一种前体材料的工艺量和/或通过临时限制沉积工艺，将覆盖层图案化成相对于衬底表面垂直的方向，并形成为后续工艺的功能层或掩模 脚步。

公开(公告)号：US07268381B2

公开(公告)日：2007-09-11

申请号：US10486758

申请日：2002-07-12

申请人： Albert Birner ,  Matthias Goldbach ,  Till Schlösser

发明人： Albert Birner ,  Matthias Goldbach ,  Till Schlösser

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876

摘要： The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

摘要翻译： 沟槽电容器的上电容器电极通过管状的单晶Si接触形成区域连接到选择晶体管的外延生长的源极/漏极区域。 栅极电极层在晶体管周围具有椭圆形外围轮廓，存储单元的栅极电极层的椭圆形外围轮廓沿着字线排列成一行形成重叠区域，以增加堆积密度。

公开(公告)号：US20070155102A1

公开(公告)日：2007-07-05

申请号：US11320489

申请日：2005-12-29

申请人： Matthias Goldbach ,  Jurgen Holz

发明人： Matthias Goldbach ,  Jurgen Holz

IPC分类号： H01L21/336

CPC分类号： H01L27/10894 ,  H01L21/268

摘要： Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

摘要翻译： 描述了制造集成电路，特别是动态随机存取存储器的方法。 在半导体衬底上形成存储单元之后，提供镜层，所述镜层覆盖存储单元。 然后形成与所述镜层所覆盖的所述存储器单元相邻的逻辑器件，所述逻辑器件的形成包括通过辐射退火激活掺杂剂区域中的掺杂剂，所述辐射由所述镜层反射。 在至少部分地去除镜层之后; 形成存储单元和逻辑器件的布线。

公开(公告)号：US07132337B2

公开(公告)日：2006-11-07

申请号：US11017194

申请日：2004-12-20

申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

摘要翻译： 电荷捕获区域布置在栅电极的下边缘下方彼此分离。 源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。 自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。

公开(公告)号：US07078748B2

公开(公告)日：2006-07-18

申请号：US10865763

申请日：2004-06-14

申请人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

发明人： Matthias Goldbach ,  Frank Jakubowski ,  Ralf Koepe ,  Chao-Wen Lay ,  Kristin Schupke ,  Michael Schmidt ,  Cheng-Chih Huang

IPC分类号： H01L27/148

CPC分类号： H01L21/28044

摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

摘要翻译： 通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中， 过渡金属是钛，钽或钴。 对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。 界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。 封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。 在将多晶硅层图案化之前打开氮化物衬垫。 作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。 提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。