公开(公告)号：US20110285445A1

公开(公告)日：2011-11-24

申请号：US12782064

申请日：2010-05-18

Applicant: Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Ming-Chieh Huang ,  Chiang Pu ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03L5/00 ,  H03B5/30 ,  H02K33/00

CPC classification number: H03B5/30

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract translation: 一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

公开(公告)号：US06165826A

公开(公告)日：2000-12-26

申请号：US581243

申请日：1995-12-29

Applicant: Robert S. Chau ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Leopoldo D. Yau

Inventor： Robert S. Chau ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Leopoldo D. Yau

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

Abstract translation: 一种具有低电阻超浅尖端区域的新型晶体管及其在互补金属氧化物半导体（CMOS）工艺中制造的方法。 根据本发明的优选方法，在具有第一导电类型的半导体衬底的第一部分上形成第一栅极电介质和第一栅电极，并且在第二栅极电极上形成第二栅极电介质和所述栅电极 具有第二导电类型的半导体衬底的部分。 在包括第一栅电极的半导体衬底的第一部分之上以及包括第二栅电极的半导体衬底的第二部分之上形成氮化硅层。 从硅衬底的第二部分和第二栅电极的顶部去除氮化硅层，从而形成与第二栅电极的相对侧相邻的第一对氮化硅间隔物。 然后在半导体衬底的第二部分中与第一对侧壁间隔件对准地形成一对凹部。 然后在凹部中形成选择性淀积的半导体材料。

公开(公告)号：US5488003A

公开(公告)日：1996-01-30

申请号：US40673

申请日：1993-03-31

Applicant: Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

Inventor： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

Abstract: A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

Abstract translation: 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。

公开(公告)号：US09134360B2

公开(公告)日：2015-09-15

申请号：US13547101

申请日：2012-07-12

Applicant: Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei

IPC: H03L5/00 ,  G01R31/26

CPC classification number: G01R31/2621

Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

Abstract translation: 电路具有包括第一电阻器和与第一电阻器并联耦合的第一和第二晶体管的第一电路模块。 第一电阻器和第一和第二晶体管在第一节点耦合在一起。 当第一节点的电压从第一电压增加到第二电压时，跨第一电路模块的等效电阻增加，并且第一电路模块上的等效电阻随着第一节点的电压从第二电压增加而减小 到第三电压。

公开(公告)号：US08896352B2

公开(公告)日：2014-11-25

申请号：US13278742

申请日：2011-10-21

Applicant: Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

Inventor： Ming-Chieh Huang ,  Tao Wen Chung ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Yuwen Swei ,  Chiang Pu

IPC: H03K3/00

CPC classification number: H03H11/44 ,  H01S5/0427 ,  H04B10/504

Abstract: A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

Abstract translation: 驱动器包括具有至少一个输入节点和至少一个第一输出节点的第一驱动器级。 第一驱动级包括邻近于至少一个第一输出节点设置的T型线圈结构。 T型线圈结构包括第一组电感器，每个电感器可操作以提供第一电感。 第二组电感器以并行方式与第一组电感器电耦合。 第二组电感器可操作以提供第二电感。 第二驱动级与第一驱动器级电耦合。

公开(公告)号：US08835246B2

公开(公告)日：2014-09-16

申请号：US13035533

申请日：2011-02-25

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh

IPC: H01L27/088 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.

Abstract translation: 形成集成电路的方法包括在衬底上形成至少一个晶体管。 所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。 工作功能金属层设置在第一栅极电介质结构上。 导电层设置在功函数金属层上。 源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。 在衬底上形成至少一个电阻器结构。 所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。 至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

公开(公告)号：US08816732B2

公开(公告)日：2014-08-26

申请号：US13530136

申请日：2012-06-22

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: H03L7/06

CPC classification number: H03L7/103 ,  H03L7/097 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/18 ,  H03L2207/06

Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.

Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。

公开(公告)号：US20140038085A1

公开(公告)日：2014-02-06

申请号：US13562436

申请日：2012-07-31

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Tsung-Ching (Jim) Huang ,  Fu-Lung Hsueh

IPC: G06F17/50 ,  G03F1/68

CPC classification number: G03F7/70466 ,  G03F7/70433 ,  G06F17/5077

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract translation: 本公开的一些方面提供了一种自动平衡多个图案化层的掩模未对准的方法，以最小化掩模未对准的后果。 在一些实施例中，该方法定义了IC布局内的一个或多个双图案化层的布线网格。 路由网格具有沿着第一方向延伸的多个垂直网格线和沿着第二正交方向延伸的多个水平网格线。 在给定方向（例如，水平和垂直方向）上布线网格的交替线被分配不同的颜色。 然后双重图案化层上的形状沿着布线网格以不同颜色的网格线之间交替的方式布线。 通过以这种方式进行布线，减少了由掩模未对准引起的电容耦合的变化。

公开(公告)号：US20140028407A1

公开(公告)日：2014-01-30

申请号：US13558670

申请日：2012-07-26

Applicant: Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

Inventor： Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Ming-Chieh Huang ,  Tsung-Ching Huang ,  Fu-Lung Hsueh

IPC: H03B5/12

CPC classification number: G06F1/10 ,  H03B5/12 ,  H03B5/32 ,  H03K5/15

Abstract: The present disclosure relates to a resonant clock system having a driver component, a clock load capacitor, and a reconfigurable inductor array. The driver component generates a driven input signal. The clock load capacitor is configured to receive the driven input signal. The inductor array is configured to have an effective inductance according to a selected frequency. The inductor array also generates a resonant signal at the selected frequency using the effective inductance.

Abstract translation: 本公开涉及具有驱动器部件，时钟负载电容器和可重构电感器阵列的谐振时钟系统。 驱动器组件产生驱动输入信号。 时钟负载电容器被配置为接收驱动输入信号。 电感器阵列被配置为具有根据选定频率的有效电感。 电感器阵列还使用有效电感在选定频率处产生谐振信号。

公开(公告)号：US08610421B2

公开(公告)日：2013-12-17

申请号：US12976504

申请日：2010-12-22

Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin

Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Chih-Chang Lin

IPC: G05F1/648

CPC classification number: G05F1/648 ,  G11C5/147 ,  H02M3/158

Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.

Abstract translation: 电流发生器包括具有布置为耦合到输入电压的负极端子的运算放大器，具有彼此连接的至少一个可调电阻器的电阻选择电路和至少一个功率晶体管。 所述至少一个功率晶体管的栅极耦合到所述运算放大器的输出，并且所述至少一个功率晶体管的漏极耦合到所述至少一个可调电阻器或负载。 电阻选择电路被配置为基于用于从运算放大器的正极端子耦合的输入电压来选择至少一个可调电阻器的节点。 所述至少一个可调电阻器被配置为基于电源电压或参考电阻器的电流来调整电阻设置以控制电流发生器的电流水平。