利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.032 秒)

    Virtual ground memory array and method therefor
    23.
    发明授权
    Virtual ground memory array and method therefor 有权
    虚拟地面存储器阵列及其方法

    公开(公告)号：US07518179B2

    公开(公告)日：2009-04-14

    申请号：US10961295

    申请日：2004-10-08

    申请人： Craig T. Swift ,  Gowrishankar L. Chindalore ,  Laureen H. Parker

    发明人： Craig T. Swift ,  Gowrishankar L. Chindalore ,  Laureen H. Parker

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  Y10S438/926 ,  Y10S438/962

    摘要： A virtual ground memory array (VGA) is formed by a storage layer over a substrate with a conductive layer over the storage layer. The conductive layer is opened according to a patterned photoresist layer. The openings are implanted to form source/drain lines in the substrate, then filled with a layer of dielectric material. Chemical mechanical polishing (CMP) is then performed until the top of the conductive layer is exposed. This leaves dielectric spacers over the source/drain lines and conductive material between the dielectric spacers. Word lines are then formed over the conductive material and the dielectric spacers. As an alternative, instead of using a conductive layer, a sacrificial layer is used that is removed after the CMP step. After removing the sacrificial portions, the word lines are formed. In both cases, dielectric spacers reduce gate/drain capacitance and the distance from substrate to gate is held constant across the channel.

    摘要翻译： 虚拟接地存储器阵列（VGA）由存储层上的存储层形成在衬底上，在存储层上方具有导电层。 根据图案化的光致抗蚀剂层打开导电层。 注入开口以在衬底中形成源极/漏极线，然后填充一层电介质材料。 然后进行化学机械抛光（CMP），直到暴露导电层的顶部。 这使得源极/漏极线之间的电介质间隔物和电介质间隔物之间​​的导电材料留下。 然后在导电材料和电介质间隔物上形成字线。 作为替代，代替使用导电层，使用在CMP步骤之后去除的牺牲层。 在去除牺牲部分之后，形成字线。 在这两种情况下，介质间隔物减少了栅极/漏极电容，并且从衬底到栅极的距离在通道上保持恒定。

    Electronic device including an array and process for forming the same
    24.
    发明授权
    Electronic device including an array and process for forming the same 有权
    包括阵列的电子设备及其形成方法

    公开(公告)号：US07399675B2

    公开(公告)日：2008-07-15

    申请号：US11079674

    申请日：2005-03-14

    申请人： Gowrishankar L. Chindalore ,  Craig T. Swift

    发明人： Gowrishankar L. Chindalore ,  Craig T. Swift

    IPC分类号： H01L21/336

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  Y10S438/926 ,  Y10S438/962

    摘要： An electronic device can include an NVM array, wherein portions of word lines are formed within trenches. Insulating features are formed over heavily doped regions within the substrate. In one embodiment, charge storage stacks and a control gate electrode layer can be formed and substantially fill the trench. The insulating features help to reduce capacitive coupling between the heavily doped regions and the control gate electrode layer. In a particular embodiment, the insulating features are recessed from a top surface of a layer outside the trenches. The control gate electrode layer can form a substantially continuous electrical path along the lengths of the word lines. This particular embodiment substantially eliminates the formation of stringers or other residual etching artifacts from the control gate electrode layer within the array. A process can be performed to form the electronic device.

    摘要翻译： 电子设备可以包括NVM阵列，其中字线的部分形成在沟槽内。 绝缘特征形成在衬底内的重掺杂区域上。 在一个实施例中，可以形成电荷存储堆叠和控制栅电极层，并且基本上填充沟槽。 绝缘特征有助于减少重掺杂区域和控制栅极电极层之间的电容耦合。 在特定实施例中，绝缘特征从沟槽外部的层的顶表面凹陷。 控制栅极电极层可以沿着字线的长度形成基本上连续的电路径。 该特定实施例基本上消除了阵列内的控制栅极电极层的桁条或其他残余蚀刻伪影的形成。 可以执行处理以形成电子设备。

    Programmable structure including discontinuous storage elements and spacer control gates in a trench
    25.
    发明授权
    Programmable structure including discontinuous storage elements and spacer control gates in a trench 有权
    可编程结构包括沟槽中的不连续存储元件和间隔物控制栅极

    公开(公告)号：US07394686B2

    公开(公告)日：2008-07-01

    申请号：US11188585

    申请日：2005-07-25

    申请人： Craig T. Swift ,  Gowrishankar L. Chindalore

    发明人： Craig T. Swift ,  Gowrishankar L. Chindalore

    IPC分类号： G11C11/34

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

    摘要： A semiconductor storage cell includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.

    摘要翻译： 半导体存储单元包括限定在半导体衬底中的第一和第二沟槽下面的第一和第二源极/漏极区域。 沟槽的侧壁衬有电荷存储堆叠，其包括不连续存储元件（DSE）层，其优选为硅纳米晶体。 间隔物控制栅极位于与沟槽侧壁上的电荷存储堆叠相邻的沟槽中。 沟槽深度超过间隔物高度，使得在间隔物的顶部和基底的顶部之间存在间隙。 连续选择栅极层覆盖在第一沟槽上。 该间隙通过加速基本上垂直于沟槽侧壁行进的电子来促进与间隙相邻的DSE的弹道编程。 存储单元可以采用热载流子注入编程来编程靠近源/漏区的DSE的一部分。

    Programming and erasing structure for a floating gate memory cell and method of making
    27.
    发明授权
    Programming and erasing structure for a floating gate memory cell and method of making 有权
    浮动存储单元的编程和擦除结构及其制作方法

    公开(公告)号：US07183161B2

    公开(公告)日：2007-02-27

    申请号：US10944244

    申请日：2004-09-17

    申请人： Gowrishankar L. Chindalore ,  Craig T. Swift

    发明人： Gowrishankar L. Chindalore ,  Craig T. Swift

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

    摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.

    摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。

    Memory with multiple state cells and sensing method
    30.
    发明授权
    Memory with multiple state cells and sensing method 有权
    具有多状态单元和感测方式的存储器

    公开(公告)号：US06847548B2

    公开(公告)日：2005-01-25

    申请号：US10601256

    申请日：2003-06-20

    申请人： Craig T. Swift ,  Michael A. Sadd

    发明人： Craig T. Swift ,  Michael A. Sadd

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0491 ,  G11C16/0475

    摘要： A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.

    摘要翻译： 存储器具有由在通道和控制栅极之间具有两个电荷存储区域的晶体管组成的阵列。 每个位由来自不同晶体管的两个电荷存储区组成。 首先擦除所有存储位置，然后写入构成该位的电荷存储位置之一，写入一位。 每一位识别一对电荷存储单元，一个被擦除，另一个编程。 通过比较存储在构成该位的两个电荷存储位置中的电荷来读取该位的逻辑状态。 该比较通过产生表示两个电荷存储位置中存在的电荷的信号来实现。 这些信号然后被耦合到用作比较器的读出放大器。 这避免了许多与固定参考比较的问题。