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    Replication of a first interface onto a second interface and related systems, methods, and devices
    21.
    发明授权
    Replication of a first interface onto a second interface and related systems, methods, and devices 有权

    公开(公告)号：US11067628B2

    公开(公告)日：2021-07-20

    申请号：US16577267

    申请日：2019-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Chiaki Dono ,  Chikara Kondo ,  Ryo Fujimaki

    IPC: G01R31/00 ,  G01R31/3177 ,  G11C29/12 ,  H01L25/18 ,  G11C11/4093

    Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

    REPLICATION OF A FIRST INTERFACE ONTO A SECOND INTERFACE AND RELATED SYSTEMS, METHODS, AND DEVICES
    22.
    发明申请
    REPLICATION OF A FIRST INTERFACE ONTO A SECOND INTERFACE AND RELATED SYSTEMS, METHODS, AND DEVICES 有权

    公开(公告)号：US20210088583A1

    公开(公告)日：2021-03-25

    申请号：US16577267

    申请日：2019-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Chiaki Dono ,  Chikara Kondo ,  Ryo Fujimaki

    IPC: G01R31/3177 ,  G11C11/4093 ,  H01L25/18 ,  G11C29/12

    Abstract: Disclosed herein are systems, methods, and devices that enable access to a first interface control circuit via test probes of a second interface. In some embodiments a memory device includes a first interface including first ports that are inaccessible to a test probe. The memory device also includes a first interface control circuit configured to control operation of the first interface. The memory device further includes a second interface including second ports. At least a portion of the second ports include test pads that are accessible to the test probe. In addition, the memory device includes a multiplexer configured to operably couple the first interface and at least a portion of the second interface to the first interface control circuit. The multiplexer is configured to selectively enable test probe access to the first interface control circuit via the test pads.

    Memory device with write data bus control
    23.
    发明授权
    Memory device with write data bus control 有权

    公开(公告)号：US10943625B2

    公开(公告)日：2021-03-09

    申请号：US16721515

    申请日：2019-12-19

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

    IPC: G11C7/10 ,  G11C19/28 ,  G11C7/22 ,  G11C16/32

    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

    Switching reduction bus using data bit inversion
    24.
    发明授权
    Switching reduction bus using data bit inversion 有权

    公开(公告)号：US10915487B2

    公开(公告)日：2021-02-09

    申请号：US16553552

    申请日：2019-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Akinori Funahashi ,  Chikara Kondo

    IPC: G06F13/42 ,  G11C8/18 ,  G11C5/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/02

    Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

    MEMORY DEVICE WITH WRITE DATA BUS CONTROL
    27.
    发明申请
    MEMORY DEVICE WITH WRITE DATA BUS CONTROL 审中-公开

    公开(公告)号：US20190122708A1

    公开(公告)日：2019-04-25

    申请号：US16225303

    申请日：2018-12-19

    Applicant: Micron Technology, Inc.

    Inventor： Chikara Kondo ,  Tomoyuki Shibata ,  Chiaki Dono ,  Seiji Narui ,  Minehiko Uehara ,  Taihei Shido ,  Homare Sato

    IPC: G11C7/10 ,  G11C7/22 ,  G11C19/28

    Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal.

    STACK ACCESS CONTROL FOR MEMORY DEVICE
    28.
    发明申请
    STACK ACCESS CONTROL FOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180341575A1

    公开(公告)日：2018-11-29

    申请号：US15606956

    申请日：2017-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Seiji Narui ,  Homare Sato ,  Chikara Kondo

    IPC: G06F12/02 ,  H01L23/522

    CPC classification number: G06F12/02 ,  G06F2212/1016 ,  G06F2212/1028 ,  H01L23/5226

    Abstract: An example apparatus includes a first semiconductor chip and a second semiconductor chip; and a first via and a plurality of second vias coupling the first semiconductor chip and the second semiconductor chip. The first semiconductor chip provides a first timing signal to the first via and further provides first data responsive to the first timing signal to the plurality of second vias. The second semiconductor chip receives the first timing signal from the first via and the first data from the plurality of second vias and further provides the first data responsive to the first timing signal, when the first semiconductor chip is designated, and provides a second timing signal and further provides second data responsive to the second timing signal, when the second semiconductor chip is designated.

    SEMICONDUCTOR DEVICE INCLUDING SPIRAL DATA PATH
    30.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING SPIRAL DATA PATH 有权
    包括螺旋数据路径的半导体器件

    公开(公告)号：US20150213860A1

    公开(公告)日：2015-07-30

    申请号：US14607858

    申请日：2015-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Seiji Narui ,  Chikara Kondo

    IPC: G11C7/22 ,  H01L25/065 ,  G11C7/10 ,  G11C5/02 ,  G11C5/06

    CPC classification number: G11C7/22 ,  G11C5/02 ,  G11C5/063 ,  G11C7/10 ,  G11C11/4097 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.

    Abstract translation: 本公开中公开的半导体器件包括形成在半导体衬底的第一表面上的第一端子，形成在与第一表面相对的半导体衬底的第二表面上方的第二端子，穿过半导体的第一贯穿衬底通孔（TSV） 基板和先进先出（FIFO）电路，其中第一TSV和FIFO电路串联耦合在第一端子和第二端子之间。

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