公开(公告)号：US20230109794A1

公开(公告)日：2023-04-13

申请号：US18079515

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C13/00

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

公开(公告)号：US20220392527A1

公开(公告)日：2022-12-08

申请号：US17880804

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Corrado Villa ,  Ferdinando Bedeschi ,  Paolo Fantini

IPC: G11C13/00 ,  H01L45/00

Abstract: Methods, systems, and devices for voltage equalization for pillars of a memory array are described. In some examples, a memory array may be configured with conductive pillars that are each coupled with a respective set of memory cells, and may be selectively coupled with an access line. To support a dissipation or equalization of charge from unselected pillars, the memory array may be configured with a material layer or level that provides a dissipative coupling, such as a coupling having a relatively high resistance or a degree of capacitance, with a ground voltage or other voltage source (e.g., to support a passive equalization). Additionally, or alternatively, a memory array may be configured to support an active dissipation of accumulated charge or voltage by selectively coupling pillars that have been operated in a floating condition with a ground voltage or other voltage source (e.g., to perform a dynamic equalization).

公开(公告)号：US11205469B2

公开(公告)日：2021-12-21

申请号：US16509916

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Stefan Frederik Schippers ,  Christophe Vincent Antoine Laurent ,  Corrado Villa

IPC: G06F1/3296 ,  G11C11/4074 ,  G11C11/406

Abstract: Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced.

公开(公告)号：US10885957B2

公开(公告)日：2021-01-05

申请号：US16189865

申请日：2018-11-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio

IPC: G11C7/22 ,  G06F13/16 ,  G11C7/10

Abstract: Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.

公开(公告)号：US10529428B2

公开(公告)日：2020-01-07

申请号：US16388501

申请日：2019-04-18

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C7/00 ,  G11C16/10 ,  G11C13/00 ,  G11C8/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US10424347B2

公开(公告)日：2019-09-24

申请号：US15843195

申请日：2017-12-15

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Corrado Villa

IPC: G11C7/00 ,  G11C5/14 ,  G06F13/16 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：US10418085B2

公开(公告)日：2019-09-17

申请号：US15655675

申请日：2017-07-20

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Corrado Villa

IPC: G11C11/22 ,  G06F1/3296 ,  G06F1/3234 ,  G06F1/3287

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. An electronic memory device may include a plurality of plate portions separated by a plurality of segmentation lines, which may be oriented in a plane parallel to rows of a memory array or columns of the memory array, or both. The segmented plate may be employed instead of a single plate for the array. The one or more plate portions may be energized during access operations of a ferroelectric cell in order to create a voltage different across the cell or to facilitate changing the charge of the cell. Each of the plate portions may include one or more memory cells. The memory cells on a plate portion may be read from or written to after the plate portion is activated by a plate driver.

公开(公告)号：US20190035470A1

公开(公告)日：2019-01-31

申请号：US16059775

申请日：2018-08-09

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C13/00 ,  G11C8/08

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

公开(公告)号：US20190012173A1

公开(公告)日：2019-01-10

申请号：US16105846

申请日：2018-08-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Graziano Mirichigni ,  Corrado Villa ,  Luca Porzio ,  Chee Weng Tan ,  Sebastien Lemarie ,  Andre Kindworth

IPC: G06F9/30 ,  G11C13/00 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10

Abstract: Apparatuses and methods for performing memory operations are described. An example apparatus includes a memory operation controller. The memory operation controller is configured to receive memory instructions and decode the same to provide internal signals for performing memory operations for the memory instructions. The memory operation controller is further configured to provide information indicative of a time for a variable latency period of a memory instruction during the variable latency period. In an example method, a write instruction and an address to which write data is to be written is received at a memory and an acknowledgement indicative of an end of a variable latency period for the write instruction is provided. After waiting a variable bus turnaround after the acknowledgement, write data for the write instruction is received.

公开(公告)号：US20170256319A1

公开(公告)日：2017-09-07

申请号：US15598103

申请日：2017-05-17

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C13/00 ,  G11C16/34 ,  G11C16/32 ,  G11C8/10

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.