公开(公告)号：US11915758B2

公开(公告)日：2024-02-27

申请号：US18095049

申请日：2023-01-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.

公开(公告)号：US20240006001A1

公开(公告)日：2024-01-04

申请号：US18369479

申请日：2023-09-18

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C16/26 ,  G11C7/1084 ,  G11C7/1057 ,  G11C16/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US20230325323A1

公开(公告)日：2023-10-12

申请号：US18178105

申请日：2023-03-03

Applicant: Micron Technology, Inc.

Inventor： Sushanth Bhushan ,  Dheeraj Srinivasan

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: Control logic in a memory device executes a first programming operation to program the set of memory cells to a set of programming levels. A first cache ready signal is generated, the first cache ready signal indicating to a host system to send first data associated with a second programming operation to an input/output (I/O) data cache of the memory device. A first encoded data value and a second encoded data value associated with each memory cell of the set of memory cells are generated. A second cache ready signal is generated, the second cache ready signal indicating to the host system to send second data associated with the next programming operation to the I/O data cache. The first data associated with the second programming operation is caused to be stored in a third data cache of the cache storage. A third cache ready signal is generated, the third cache ready signal indicating to the host system to send third data associated with the second programming operation to the I/O data cache.

公开(公告)号：US20230305717A1

公开(公告)日：2023-09-28

申请号：US18125279

申请日：2023-03-23

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Luanming Deng

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system includes a memory device including a memory array and control logic operatively coupled with the memory array. The memory array includes a target cell connected to a target wordline, a first cell connected to a first adjacent wordline adjacent to the target wordline, and a second cell connected to a second adjacent wordline adjacent to the target wordline. The control logic performs operations including causing a read to be performed with respect to the first cell to obtain an adjacent wordline read result, storing the adjacent wordline read result using a first set of page buffers, causing an incremental read to be performed with respect to the second cell and a first bin to obtain a first incremental read result, and storing the first incremental read result using a second set of page buffers.

公开(公告)号：US11688466B2

公开(公告)日：2023-06-27

申请号：US17678960

申请日：2022-02-23

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/26

Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The circuit coupled to the dynamic memory element can perform a first operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

公开(公告)号：US20230059543A1

公开(公告)日：2023-02-23

申请号：US17887940

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

IPC: G06F3/06

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

公开(公告)号：US11562791B1

公开(公告)日：2023-01-24

申请号：US17396825

申请日：2021-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

公开(公告)号：US11276470B2

公开(公告)日：2022-03-15

申请号：US16947091

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and one or more bitline driver circuits coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The one or more bitline driver circuits can perform a first pre-charging operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

公开(公告)号：US20210181955A1

公开(公告)日：2021-06-17

申请号：US17187066

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Dheeraj Srinivasan ,  Terry M. Grunzke

IPC: G06F3/06 ,  G06F12/0811

Abstract: The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

公开(公告)号：US10977186B2

公开(公告)日：2021-04-13

申请号：US15819941

申请日：2017-11-21

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Michael G. Miller ,  Xiaoxiao Zhang ,  Jung Sheng Hoei

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/56 ,  G06F11/07

Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.