公开(公告)号：US09530683B2

公开(公告)日：2016-12-27

申请号：US14534454

申请日：2014-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： John Hopkins ,  James Matthew ,  Jie Sun ,  Gordon Haller

IPC: H01L21/336 ,  H01L21/762 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L27/11524 ,  H01L27/1157

Abstract: An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.

Abstract translation: 一个实施例包括在半导体中在第一和第二有源区之间形成隔离区，通过去除隔离区的一部分形成第一和第二有源区之间的开口，以及在该开口内形成电介质塞， 在第一和第二有源区之间并且使得电介质塞的一部分延伸到第一和第二有源区的上表面之下。 电介质插塞可以由对于特定的各向同性的去除化学物质具有比隔离区域的电介质材料更低的去除速率的电介质材料形成。

公开(公告)号：US09431410B2

公开(公告)日：2016-08-30

申请号：US14069574

申请日：2013-11-01

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/66825 ,  H01L29/7889

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract translation: 公开了形成一串存储单元的方法，具有一串存储单元的装置和系统。 用于形成一串存储单元的一种这样的方法在衬底上形成源材料。 可以在源材料上形成封盖材料。 可以在封盖材料之上形成选择栅极材料。 多个电荷存储结构可以在选择栅极材料上以多个交替层级的控制栅极和绝缘体材料形成。 可以通过控制栅极和绝缘体材料，选择栅极材料和封盖材料的多个交替层级形成第一开口。 通道材料可以沿着第一开口的侧壁形成。 通道材料的厚度小于第一开口的宽度，使得第二开口由半导体沟道材料形成。

公开(公告)号：US09362300B2

公开(公告)日：2016-06-07

申请号：US14509621

申请日：2014-10-08

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/14 ,  G11C16/34 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有多层存储器单元和相关控制门的装置和方法。 一种方法包括形成具有交替的导体材料和电介质材料的第一甲板和包含延伸穿过导体材料和电介质材料的材料的孔。 所述方法还可以包括在所述孔的扩大部分中形成牺牲材料并在所述第一甲板上形成第二层记忆单元。 描述附加的装置和方法。

公开(公告)号：US20160049417A1

公开(公告)日：2016-02-18

申请号：US14925589

申请日：2015-10-28

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/115 ,  H01L29/66

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

Abstract translation: 垂直存储器中的浮动存储单元。 控制栅极形成在介电材料的第一层和第二层电介质材料之间。 浮动栅极形成在介电材料的第一层和第二层介质材料之间，其中浮动栅极包括朝向控制栅极延伸的突起。 在浮置栅极和控制栅极之间形成电荷阻挡结构，其中电荷阻挡结构的至少一部分围绕突起卷绕。

公开(公告)号：US20250109954A1

公开(公告)日：2025-04-03

申请号：US18775052

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Mohad Baboli ,  John Hopkins

IPC: G01C21/34 ,  B60W60/00 ,  G06Q30/0251 ,  G06Q30/0273 ,  G06Q50/47

Abstract: A system and method for optimizing routes for an autonomous vehicle ride service based on business promotions and incentives. A vehicle routing service identifies multiple possible routes between a rider's pick-up and drop-off locations that meet time and distance requirements. For each route, an expected monetary value is calculated based on promotions from businesses located near the route. Businesses provide promotions with bid values via an integrated promotion management platform. The route with the highest expected value based on associated promotion bid values is selected and provided to the autonomous vehicle. Promotion content is transmitted to vehicle displays or the rider's mobile device. The rider can accept offers to re-route to a business. The system continually evaluates new promotions for additional revenue opportunities. By optimizing routes based on promotions and incentives, the system maximizes value for riders, businesses, and the ride service.

公开(公告)号：US20230335500A1

公开(公告)日：2023-10-19

申请号：US18214911

申请日：2023-06-27

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  Yiping Wang ,  Jordan D. Greenlee ,  John Hopkins

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76895 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

公开(公告)号：US20230326793A1

公开(公告)日：2023-10-12

申请号：US18200852

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Kar Wui Thong ,  Harsh Narendrakumar Jain ,  John Hopkins

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76897 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a dielectric structure formed in a slit, the slit extending through the levels of conductive materials and the levels of dielectric materials, the dielectric structure separating the levels of conductive materials and the levels of dielectric materials into a first portion and a second portion; first conductive structures located over and coupled to respective pillars of the first memory cell strings; second conductive structures located over and coupled to respective pillars of the second memory cell strings; and a conductive line contacting the dielectric structure, a conductive structure of the first conductive structures, and a conductive structure of the second conductive structures.

公开(公告)号：US11088168B2

公开(公告)日：2021-08-10

申请号：US16834291

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US10608004B2

公开(公告)日：2020-03-31

申请号：US16028111

申请日：2018-07-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US20190288002A1

公开(公告)日：2019-09-19

申请号：US16419736

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  H01L27/11529 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11524 ,  G11C16/34 ,  G11C16/14 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.