公开(公告)号：US20170345511A1

公开(公告)日：2017-11-30

申请号：US15449426

申请日：2017-03-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Andrea D'Alessandro ,  Violante Moschiano ,  Mattia Cichocki ,  Michele Incarnati ,  Federica Paolini

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/14

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.

公开(公告)号：US20170270983A1

公开(公告)日：2017-09-21

申请号：US15614072

申请日：2017-06-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Viloante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US09343169B2

公开(公告)日：2016-05-17

申请号：US14162278

申请日：2014-01-23

Applicant: Micron Technology, Inc.

Inventor： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati ,  Violante Moschiano

IPC: G11C8/00 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C27/02

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C27/02 ,  G11C2211/5642 ,  G11C2211/5646

Abstract: Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.

Abstract translation: 例如，公开了存储器，存储器件和系统的编程方法。 在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。 在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

公开(公告)号：US09245646B2

公开(公告)日：2016-01-26

申请号：US14528251

申请日：2014-10-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Giovanni Santin ,  Michele Incarnati

IPC: G11C11/34 ,  G11C16/34 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/26

Abstract: Methods for program verifying a memory cell include generating an access line voltage in response to a count and applying the access line voltage to a control gate of the memory cell, and generating a pass signal in response to the access line voltage activating the memory cell. Methods further include comparing at least a portion of the count to an indication of a desired threshold voltage of the memory cell, and when the at least a portion of the count matches the indication of the desired threshold voltage of the memory cell, determining if the pass signal is present. Methods further include generating a signal indicative of a desire to inhibit further programming of the memory cell if the pass signal is present when the match is indicated.

Abstract translation: 用于程序验证存储器单元的方法包括响应于计数产生访问线电压并将存取线电压施加到存储器单元的控制栅极，并且响应于启动存储器单元的存取线电压而产生通过信号。 方法还包括将计数的至少一部分与存储器单元的期望阈值电压的指示进行比较，并且当计数的至少一部分与存储器单元的期望阈值电压的指示匹配时，确定是否 存在通过信号。 如果在指示匹配时存在通过信号，那么方法还包括产生指示禁止进一步编程存储器单元的信号的信号。

公开(公告)号：US20240231670A1

公开(公告)日：2024-07-11

申请号：US18509587

申请日：2023-11-15

Applicant: Micron Technology, Inc.

Inventor： Angelo Covello ,  Claudia Ciaschi ,  Michele Incarnati ,  Tommaso Vali

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory device includes a local memory to store operational data and comparison logic operatively coupled with the local memory. The comparison logic, upon initialization of the memory device, compares, to detect any errors in the operational data, one copy of a first copy pair with one copy of a second copy pair of the operational data, the first copy pair including a first copy and an inverted first copy and the second copy pair including a second copy and an inverted second copy of the operational data. The comparison logic further reports an error in response to detecting the first copy pair does not match the second copy pair.

公开(公告)号：US11550717B2

公开(公告)日：2023-01-10

申请号：US16548754

申请日：2019-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Andrea Giovanni Xotta ,  Umberto Siciliani ,  Luca DeSantis ,  Michele Incarnati

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/02

Abstract: Apparatuses and methods for concurrently accessing different memory planes are disclosed herein. An example apparatus may include a controller associated with a queue configured to maintain respective information associated with each of a plurality of memory command and address pairs. The controller is configured to select a group of memory command and address pairs from the plurality of memory command and address pairs based on the information maintained by the queue. The example apparatus further includes a memory configured to receive the group of memory command and address pairs. The memory is configured to concurrently perform memory access operations associated with the group of memory command and address pairs.

公开(公告)号：US10409673B2

公开(公告)日：2019-09-10

申请号：US15414699

申请日：2017-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C29/52

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.

公开(公告)号：US20180366167A1

公开(公告)日：2018-12-20

申请号：US16109628

申请日：2018-08-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

公开(公告)号：US10134481B2

公开(公告)日：2018-11-20

申请号：US15449426

申请日：2017-03-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Andrea D'Alessandro ,  Violante Moschiano ,  Mattia Cichocki ,  Michele Incarnati ,  Federica Paolini

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

Abstract: Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.

公开(公告)号：US20160048343A1

公开(公告)日：2016-02-18

申请号：US14461152

申请日：2014-08-15

Applicant: Micron Technology, Inc.

Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

IPC: G06F3/06

CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract translation: 本文公开了用于对不同存储器平面执行并发存储器访问操作的装置和方法。 示例性装置可以包括具有多个存储器平面的存储器阵列。 多个存储器平面中的每一个包括多个存储单元。 该装置还可以包括被配置为接收一组存储器命令和地址对的控制器。 该组存储器命令和地址对的每个存储器命令和地址对可以与多个存储器平面中的相应存储器平面相关联。 内部控制器可以被配置为与存储器命令和地址组组的存储器命令组和地址对组中的每个存储器命令和地址对相关联地执行存储器访问操作，而不管与组的对相关联的页面类型（ 例如，即使两个或多个存储器命令和地址对可以与不同的页面类型相关联）。