公开(公告)号：US20240290385A1

公开(公告)日：2024-08-29

申请号：US18409702

申请日：2024-01-10

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Shyam Surthi ,  Martin W. Popp ,  KangYoul Lee ,  Yui Shimizu

IPC: G11C16/04 ,  H01L23/528

CPC classification number: G11C16/0483 ,  H01L23/5283

Abstract: A microelectronic device comprises, a control circuitry structure comprising an active region including control logic circuitry at least partially within a semiconductive material; a bond pad on a backside of the control circuitry structure; a conductive contact vertically extending from the bond pad, through the semiconductive material, and to the control logic circuitry; and a dielectric-filled slit vertically extending into the semiconductive material and horizontally circumscribing the conductive contact, portions of the semiconductive material horizontally interposed between the conductive contact and the dielectric-filled slit. Additional microelectronic devices, memory devices, microelectronic device packages, and electronic systems are also described.

公开(公告)号：US20240071966A1

公开(公告)日：2024-02-29

申请号：US17961025

申请日：2022-10-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shyam Surthi

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Memory array structures might include a first data line selectively connected to a first plurality of memory cells, a second data line selectively connected to a second plurality of memory cells, a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line, a second dielectric containing a void extending between a second portion of the first data line and a second portion of the second data line, and a top contact overlying and in contact with the first portion of the first data line.

公开(公告)号：US20230189515A1

公开(公告)日：2023-06-15

申请号：US17549237

申请日：2021-12-13

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Shyam Surthi

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/538

CPC classification number: H01L27/11556 ,  G11C5/025 ,  H01L27/11582 ,  H01L23/5386

Abstract: A microelectronic device comprises a stack structure, a staircase structure, an etch stop material, and insulative material. The stack structure comprises conductive structures, and air gaps vertically alternating with the conductive structures. The staircase structure is within the stack structure and has steps comprising edges of at least some of the conductive structures of the stack structure. The etch stop material continuously extends over the conductive structures and at least partially defines horizontal boundaries of the air gaps. The insulative material overlies the etch stop material. Additional microelectronic devices, memory devices, electronic systems, and methods are also disclosed.

公开(公告)号：US11587948B2

公开(公告)日：2023-02-21

申请号：US17369605

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11557608B2

公开(公告)日：2023-01-17

申请号：US17393664

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/792 ,  H01L21/02 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US11296103B2

公开(公告)日：2022-04-05

申请号：US16863000

申请日：2020-04-30

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Kunal Shrotri ,  Matthew Thorum

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210233933A1

公开(公告)日：2021-07-29

申请号：US17230541

申请日：2021-04-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/792 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11556

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200373325A1

公开(公告)日：2020-11-26

申请号：US16988548

申请日：2020-08-07

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  H01L27/1157 ,  G11C16/08 ,  H01L21/02

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US09559201B2

公开(公告)日：2017-01-31

申请号：US14718785

申请日：2015-05-21

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/764 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/76232 ,  H01L21/764 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666

Abstract: Vertical memory devices comprise vertical transistors in an array region and digit lines extending in a first direction and comprising a source region or a drain region of at least some of the vertical transistors. The vertical memory devices further include word lines extending in a second direction along sidewalls of the vertical transistors and along sidewalls of columns of an oxide material in a word line end region. The wordlines extend closer to an upper surface of the vertical memory device on the sidewalls of the oxide material than on the sidewalls of the vertical transistors. Memory arrays comprising vertical transistors in an array region, digit line, and word lines are disclosed, as are memory devices comprising transistors in an array region, digit lines, and word lines.

Abstract translation: 垂直存储器件包括阵列区域中的垂直晶体管和沿第一方向延伸并且包括至少一些垂直晶体管的源极区域或漏极区域的数字线。 垂直存储器件还包括沿垂直晶体管的侧壁沿着第二方向延伸的字线，并且沿着字线端部区域中的氧化物材料的列的侧壁延伸。 字线在氧化物材料的侧壁上比垂直晶体管的侧壁更靠近垂直存储器件的上表面。 公开了包括阵列区域，数字线和字线中的垂直晶体管的存储器阵列，以及包括阵列区域，数字线和字线中的晶体管的存储器件。

公开(公告)号：US09318493B2

公开(公告)日：2016-04-19

申请号：US14502978

申请日：2014-09-30

Applicant: Micron Technology, Inc.

Inventor： Lars P. Heineck ,  Shyam Surthi ,  Jaydip Guha

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/778 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L27/10802 ,  H01L21/28132 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666 ,  H01L29/7788 ,  H01L29/7827 ,  H01L29/7841

Abstract: Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Abstract translation: 一些实施例包括存储器阵列。 存储器阵列可以在垂直取向的晶体管下面具有数字线，数字线将晶体管沿阵列的列互连。 每个单独的晶体管可以直接在单个数字线上，单个数字线完全由一个或多个含金属材料组成。 数字线可以在甲板上，电绝缘区域可以直接位于数字线和甲板之间。 一些实施例包括形成存储器阵列的方法。 可以形成多个含硅材料的线性段，以从含硅材料的基底向上延伸。 基底可以被蚀刻以在线性段下面形成含硅基底，并且基脚可以被转换成金属硅化物。 线性段可以被图案化成从金属硅化物基部向上延伸的多个垂直取向的晶体管基座。