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    Integrated Circuit Structures Comprising Conductive Vias And Methods Of Forming Conductive Vias
    23.
    发明申请
    Integrated Circuit Structures Comprising Conductive Vias And Methods Of Forming Conductive Vias 审中-公开

    公开(公告)号：US20170338181A1

    公开(公告)日：2017-11-23

    申请号：US15621329

    申请日：2017-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L27/24

    CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11582 ,  H01L27/2463 ,  H01L28/00

    Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.

    Integrated circuit structures comprising conductive vias and methods of forming conductive vias
    24.
    发明授权
    Integrated circuit structures comprising conductive vias and methods of forming conductive vias 有权

    公开(公告)号：US09704802B2

    公开(公告)日：2017-07-11

    申请号：US14838738

    申请日：2015-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/24 ,  H01L21/768

    CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11582 ,  H01L27/2463 ,  H01L28/00

    Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance. Integrated circuit structure comprising conductive vias independent of method of manufacture are disclosed.

    Semiconductor Constructions and Methods of Forming Electrically Conductive Contacts
    25.
    发明申请
    Semiconductor Constructions and Methods of Forming Electrically Conductive Contacts 有权
    形成导电触头的半导体结构和方法

    公开(公告)号：US20150303100A1

    公开(公告)日：2015-10-22

    申请号：US14788960

    申请日：2015-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H01L21/76834 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53271 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include methods of forming electrically conductive contacts. An opening is formed through an insulative material to a conductive structure. A conductive plug is formed within a bottom region of the opening. A spacer is formed to line a lateral periphery of an upper region of the opening, and to leave an inner portion of an upper surface of the plug exposed. A conductive material is formed against the inner portion of the upper surface of the plug. Some embodiments include semiconductor constructions having a conductive plug within an insulative stack and against a copper-containing material. A spacer is over an outer portion of an upper surface of the plug and not directly above an inner portion of the upper surface. A conductive material is over the inner portion of the upper surface of the plug and against an inner lateral surface of the spacer.

    Abstract translation: 一些实施例包括形成导电触点的方法。 通过绝缘材料向导电结构形成开口。 导电插塞形成在开口的底部区域内。 形成间隔件以将开口的上部区域的侧边缘排列，并且使塞子的上表面的内部部分露出。 导电材料抵靠插塞的上表面的内部形成。 一些实施例包括在绝缘堆叠内具有导电插塞并且覆盖含铜材料的半导体结构。 间隔件在塞子的上表面的外部部分上方并且不在上表面的内部的正上方。 导电材料在插塞的上表面的内部部分上并且抵靠隔离件的内侧表面。

    Arrays Of Memory Cells And Methods Of Forming An Array Of Vertically Stacked Tiers Of Memory Cells
    27.
    发明申请
    Arrays Of Memory Cells And Methods Of Forming An Array Of Vertically Stacked Tiers Of Memory Cells 审中-公开
    记忆单元阵列和形成垂直堆叠层的存储单元阵列的方法

    公开(公告)号：US20150123070A1

    公开(公告)日：2015-05-07

    申请号：US14594813

    申请日：2015-01-12

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  G11C13/0002 ,  G11C13/0011 ,  G11C2213/71 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

    Abstract translation: 存储单元的垂直堆叠层的阵列包括存储器单元的各层内的多个水平定向的接入线以及层的高度向外的多个水平定向的全局感测线。 多个选择晶体管正在层级的内侧。 多对局部第一和第二垂直线延伸穿过层。 这些对中的单独的局部第一垂直线与全球感测线之一导电连接，并且与选择晶体管之一的两个源极/漏极区之一导电连接。 对中的单独的本地第二垂直线与一个选择晶体管的两个源极/漏极区域中的另一个导电连接。 存储单元的个体包括本地第二垂直线和其中一个水平访问线和其间的可编程材料的交叉的一个。 公开了包括方法的其他方面和实现。

    Nonvolatile Memory Cells and Arrays of Nonvolatile Memory Cells
    29.
    发明申请
    Nonvolatile Memory Cells and Arrays of Nonvolatile Memory Cells 有权
    非易失性存储单元和非易失性存储单元阵列

    公开(公告)号：US20130306933A1

    公开(公告)日：2013-11-21

    申请号：US13950026

    申请日：2013-07-24

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu ,  David H. Wells

    IPC: H01L27/24

    CPC classification number: H01L27/2409 ,  G11C5/02 ,  H01L27/249 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and second electrodes. Current conductive material is in series between and with the programmable material and the select device. An array of vertically stacked tiers of such nonvolatile memory cells is disclosed. Methods of forming arrays of nonvolatile memory cells are disclosed.

    Abstract translation: 非易失性存储单元包括第一和第二电极。 可编程材料和选择装置被串联接纳在第一和第二电极之间。 当前导电材料与可编程材料和选择装置之间串联在一起。 公开了这种非易失性存储单元的垂直层叠的阵列。 公开了形成非易失性存储单元阵列的方法。

    Memory arrays
    30.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10859661B2

    公开(公告)日：2020-12-08

    申请号：US16924068

    申请日：2020-07-08

    Applicant: Micron Technology, Inc.

    Inventor： Zengtao T. Liu

    IPC: G11C11/00 ,  G01R33/58 ,  G11C7/10 ,  H01L27/24 ,  G11C13/00 ,  G11C8/14 ,  H01L45/00 ,  G01R33/12 ,  G11C5/06 ,  G11C5/02 ,  G01R33/24

    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

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