公开(公告)号：US06774655B2

公开(公告)日：2004-08-10

申请号：US10622472

申请日：2003-07-21

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06724675B2

公开(公告)日：2004-04-20

申请号：US10352985

申请日：2003-01-29

申请人： Akihiro Funyu ,  Shinya Fujioka ,  Hitoshi Ikeda ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato ,  Yasurou Matsuzaki

发明人： Akihiro Funyu ,  Shinya Fujioka ,  Hitoshi Ikeda ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato ,  Yasurou Matsuzaki

IPC分类号： G11C800

CPC分类号： G11C7/1042 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4072

摘要： A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.

摘要翻译： 为了保存数据而需要刷新的诸如DRAM的半导体存储器件提供有用于存储数据的存储部分和在刷新操作期间输出忙信号的忙信号输出部分。

公开(公告)号：US06636444B2

公开(公告)日：2003-10-21

申请号：US10057976

申请日：2002-01-29

申请人： Toshiya Uchida ,  Yasurou Matsuzaki

发明人： Toshiya Uchida ,  Yasurou Matsuzaki

IPC分类号： G11C1604

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C8/06

摘要： A semiconductor memory device has a read data line, a write data line, a data holding circuit, and a data writing circuit. The data holding circuit holds data on the write data line, and the data writing circuit writes the data held on the write data line into a memory cell. Further, a semiconductor memory device has a read data line, a write data line, and an address information holding circuit. The address information holding circuit holds address information that is input in relation to write data, and when an access occurs to the address held in the address information holding circuit, data held on the write data line is written into a memory cell corresponding to the address.

公开(公告)号：US06621283B1

公开(公告)日：2003-09-16

申请号：US09437221

申请日：1999-11-10

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Toshiya Uchida ,  Atsushi Hatakeyama ,  Kenichi Kawasaki ,  Yasuhiro Fujii

IPC分类号： G01R3102

CPC分类号： G11C29/022 ,  G11C29/02

摘要： A semiconductor device mounted on a board or the like and having a test circuit, having the function of carrying out a contact test at a low cost on the terminals of the semiconductor, is disclosed. The semiconductor device comprises a terminal test circuit for testing a state of a contact of an external terminal and a test mode control circuit unit. The test mode control circuit unit outputs a signal indicating a first operation mode upon application of a power supply voltage thereto, outputs a test mode signal to the terminal test circuit in response to a control signal input to a specific terminal such as a chip select terminal, and outputs a signal indicating a second operation mode in response to the number of times in which the level of the control signal input to the specific terminal changes. Preferably, the first operation mode is a terminal test mode, and the second operation mode is a normal operation mode. A method of testing the semiconductor device and a semiconductor integrated circuit, having the test circuit, are also disclosed.

摘要翻译： 公开了一种安装在板等上并具有测试电路的半导体器件，具有在半导体端子上以低成本进行接触测试的功能。 半导体器件包括用于测试外部端子和测试模式控制电路单元的接触状态的端子测试电路。 测试模式控制电路单元在施加电源电压时输出指示第一操作模式的信号，响应于输入到诸如芯片选择端子的特定终端的控制信号，向终端测试电路输出测试模式信号 并且响应于输入到特定终端的控制信号的电平改变的次数而输出指示第二操作模式的信号。 优选地，第一操作模式是终端测试模式，并且第二操作模式是正常操作模式。 还公开了一种测试半导体器件的方法和具有测试电路的半导体集成电路。

公开(公告)号：US06433607B1

公开(公告)日：2002-08-13

申请号：US09344810

申请日：1999-06-25

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Yasurou Matsuzaki ,  Takaaki Suzuki

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Yasurou Matsuzaki ,  Takaaki Suzuki

IPC分类号： H03K300

摘要： An input circuit has an input buffer and a detection circuit. The input buffer receives an external signal and outputs an internal signal. The detection circuit detects whether or not the external signal is provided. The input buffer outputs the internal signal when an output of the detection circuit indicates that the external signal is provided. This arrangement shortens the lock-on time of an internal circuit (synchronous circuit).

公开(公告)号：US06421285B2

公开(公告)日：2002-07-16

申请号：US09855662

申请日：2001-05-16

申请人： Yasurou Matsuzaki ,  Tsuneo Funatsu

发明人： Yasurou Matsuzaki ,  Tsuneo Funatsu

IPC分类号： G11C700

CPC分类号： G11C29/783 ,  G11C17/18 ,  G11C29/785

摘要： A semiconductor storage device includes a redundancy circuit, which replaces a defective memory cell with a redundancy memory cell. The semiconductor storage device further includes a charge pump used for programming redundancy information by performing dielectric breakdown selectively to a capacity. In addition, a redundancy control circuit included in the semiconductor storage device supplies a fixed charge to the capacity, and refreshes the capacity, thereby reproducing the redundancy information programmed by use of the charge pump. Additionally, the redundancy control unit supplies the redundancy information to a redundancy circuit.

公开(公告)号：US06194930B1

公开(公告)日：2001-02-27

申请号：US09320847

申请日：1999-05-26

申请人： Yasurou Matsuzaki ,  Masao Nakano ,  Yasuhiro Fujii

发明人： Yasurou Matsuzaki ,  Masao Nakano ,  Yasuhiro Fujii

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  H03L7/0814

摘要： The present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock. The DLL circuit comprises a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phases of the first clock against that of a second clock, generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal. The delay control circuit generates a single delay control signal, which changes by a minimum delay quantity unit a delay quantity of the variable delay circuit in a first operating period of the DLL circuit, and generates a binary delay control signal, which changes by a binary unit a delay quantity of the variable delay circuit in a second operating period that differs from the first operating period of the DLL circuit. A lock-on state can be achieved in a short time, and stable operation is possible.

摘要翻译： 本发明是一种DLL电路，其延迟第一时钟，并产生与该第一时钟具有预定相位关系的控制时钟。 DLL电路包括用于改变第一时钟的延迟的可变延迟电路; 相位比较器，用于通过将可变延迟电路的输出延迟预定时间并产生相位比较结果信号而产生的第一时钟的相位和第二时钟的相位; 以及延迟控制电路，用于向可变延迟电路提供响应于相位比较结果信号来控制该延迟量的延迟控制信号。 延迟控制电路产生单个延迟控制信号，该延迟控制信号在DLL电路的第一操作周期中以最小延迟量单位改变可变延迟电路的延迟量，并产生二进制延迟控制信号，二进制延迟控制信号由二进制 在与DLL电路的第一操作周期不同的第二操作周期中单元可变延迟电路的延迟量。 可以在短时间内实现锁定状态，并且可以稳定地操作。

公开(公告)号：US6088255A

公开(公告)日：2000-07-11

申请号：US137101

申请日：1998-08-20

申请人： Yasurou Matsuzaki ,  Takaaki Suzuki

发明人： Yasurou Matsuzaki ,  Takaaki Suzuki

IPC分类号： G11C7/22 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081 ,  G11C7/00

CPC分类号： H03L7/0805 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  H03K5/133 ,  H03L7/0814 ,  H03K2005/00104

摘要： A semiconductor device includes a variable-delay circuit which adjusts a delay of an input clock signal by changing a number of delay elements having the input clock signal passing therethrough so as to generate a delayed clock signal, and a timing-stabilization circuit which changes the number of delay elements by one stage at a time in a first condition and by more than one stage at a time in a second condition to control the delay, thereby stabilizing the delayed clock signal to a desired timing.

摘要翻译： 半导体器件包括可变延迟电路，其通过改变具有通过其中的输入时钟信号的延迟元件的数量来调节输入时钟信号的延迟，以产生延迟的时钟信号;以及定时稳定电路，其改变 延迟元件的数量在第一状态中一次一级，并且在第二状态中的一个阶段，以控制延迟，从而将延迟的时钟信号稳定到期望的定时。

公开(公告)号：US4982117A

公开(公告)日：1991-01-01

申请号：US433912

申请日：1989-11-09

申请人： Yasurou Matsuzaki ,  Yuji Tsuchimoto ,  Yoshikazu Mutoh ,  Masaki Takahashi

发明人： Yasurou Matsuzaki ,  Yuji Tsuchimoto ,  Yoshikazu Mutoh ,  Masaki Takahashi

IPC分类号： G11C11/41 ,  G11C8/18 ,  H03K5/1532

CPC分类号： G11C8/18

摘要： An address transition detector circuit detects a transition of an address signal. The address transition detector circuit has a first circuit part which includes two field effect transistors which are coupled in series and simultaneously turn ON when an address transition is detected, and a second circuit part which includes a bipolar transistor for discharging so that a transition detection signal changes its level immediately after the address transition is detected in the first circuit part.

公开(公告)号：US4646264A

公开(公告)日：1987-02-24

申请号：US505957

申请日：1983-06-20

申请人： Yasurou Matsuzaki

发明人： Yasurou Matsuzaki

IPC分类号： G11C17/00 ,  G11C17/08 ,  G11C17/18 ,  G11C11/40

CPC分类号： G11C17/18

摘要： A programmable ROM device comprising, for example, junction-shorting-type or fuse-blown-type memory cells, connected between word lines and bit lines, in which device information is written into a selected memory cell by applying a high voltage to a terminal such as a CE terminal and by applying a write-in current to the bit line connected to the selected memory cell and in which leakage of the write-in current into memory cells adjacent to the selected memory cell is prevented, thereby providing a reliable information-storing operation.

摘要翻译： 一种可编程ROM器件，其包括例如在字线和位线之间连接短路型或熔丝熔断型存储单元，其中通过向终端施加高电压将器件信息写入所选存储单元 例如CE终端，并且通过向连接到所选择的存储器单元的位线施加写入电流，并且防止写入电流泄漏到与选择的存储器单元相邻的存储器单元中，由此提供可靠的信息 储存操作。