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    Semiconductor integrated circuit memory
    3.
    发明授权
    Semiconductor integrated circuit memory 有权
    半导体集成电路存储器

    公开(公告)号：US06185149B2

    公开(公告)日：2001-02-06

    申请号：US09340147

    申请日：1999-06-28

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    IPC分类号： G11C800

    CPC分类号： G11C7/1018 ,  G11C7/1072

    摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

    摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06498522B2

    公开(公告)日：2002-12-24

    申请号：US09833045

    申请日：2001-04-12

    申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    IPC分类号： H03L700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

    摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.

    摘要翻译： 本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。 根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号 接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

    Semiconductor device with circuitry for efficient information exchange
    8.
    发明授权
    Semiconductor device with circuitry for efficient information exchange 有权
    具有用于有效信息交换的电路的半导体器件

    公开(公告)号：US07782682B2

    公开(公告)日：2010-08-24

    申请号：US10006238

    申请日：2001-12-10

    申请人： Yasurou Matsuzaki ,  Masao Taguchi

    发明人： Yasurou Matsuzaki ,  Masao Taguchi

    IPC分类号： G11C7/77

    CPC分类号： H03M5/14 ,  G11C8/10 ,  H03M7/00 ,  H03M7/30

    摘要： A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

    摘要翻译： 具有寄存器和信息产生电路的半导体器件可以减少要传输的数据，从而节省电力。 寄存器存储第一个信息。 信息生成电路响应于从设备的外部获取的信号，生成指示第一信息的哪些位将被反转的第二信息。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    10.
    发明授权
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 有权

    公开(公告)号：US06333660B2

    公开(公告)日：2001-12-25

    申请号：US09780475

    申请日：2001-02-12

    申请人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    发明人： Masao Taguchi ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki

    IPC分类号： H03K3013

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer. A switch is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the ½ phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.