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    Semiconductor memory device having an SRAM and a DRAM on a single chip
    3.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06735141B2

    公开(公告)日：2004-05-11

    申请号：US09917913

    申请日：2001-07-31

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C700

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor memory device having an SRAM and a DRAM on a single chip
    4.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06292426B1

    公开(公告)日：2001-09-18

    申请号：US09531498

    申请日：2000-03-21

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C800

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06498522B2

    公开(公告)日：2002-12-24

    申请号：US09833045

    申请日：2001-04-12

    申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Yasuharu Sato ,  Yasurou Matsuzaki

    IPC分类号： H03L700

    CPC分类号： G11C7/1084 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

    摘要： The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.

    摘要翻译： 本发明涉及一种时钟同步型半导体器件，其与时钟信号同步地接收从外部输入的输入信号。 根据本发明的半导体器件包括输入信号接收单元，其接收从外部输入的输入信号，其中接收与时钟信号同步完成; 时钟定时选择单元，用于输出时钟选择信号; 以及时钟发生单元，响应于接收到时钟选择信号和外部时钟信号，在与时钟选择信号的信号电平相对应的预定定时产生时钟信号，并将时钟信号输出到输入信号 接收单元，其中无论外部时钟信号的频率如何，都可以安全地接受输入信号。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06396758B2

    公开(公告)日：2002-05-28

    申请号：US09793603

    申请日：2001-02-27

    申请人： Hitoshi Ikeda ,  Tatsuya Kanda ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

    发明人： Hitoshi Ikeda ,  Tatsuya Kanda ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.

    摘要翻译： 具有自刷新操作的半导体存储器件包括检测电路，当检测到给定输入信号的变化时产生检测信号;以及比较器电路，将检测信号与内部产生的刷新请求信号进行比较，并生成表示 电路操作。

    Data transfer method and system
    7.
    发明授权
    Data transfer method and system 失效
    数据传输方式和系统

    公开(公告)号：US07730232B2

    公开(公告)日：2010-06-01

    申请号：US11113181

    申请日：2005-04-25

    申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

    摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

    摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。