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    Semiconductor memory device having an SRAM and a DRAM on a single chip
    3.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06735141B2

    公开(公告)日：2004-05-11

    申请号：US09917913

    申请日：2001-07-31

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C700

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor memory device having an SRAM and a DRAM on a single chip
    4.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06292426B1

    公开(公告)日：2001-09-18

    申请号：US09531498

    申请日：2000-03-21

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C800

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Data transfer method and system
    5.
    发明授权
    Data transfer method and system 失效
    数据传输方式和系统

    公开(公告)号：US07730232B2

    公开(公告)日：2010-06-01

    申请号：US11113181

    申请日：2005-04-25

    申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

    摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

    摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

    Electronic instrument and semiconductor memory device
    7.
    发明授权
    Electronic instrument and semiconductor memory device 有权
    电子仪器和半导体存储器件

    公开(公告)号：US06172938B2

    公开(公告)日：2001-01-09

    申请号：US09338597

    申请日：1999-06-23

    申请人： Takaaki Suzuki ,  Masao Taguchi ,  Kotoku Sato

    发明人： Takaaki Suzuki ,  Masao Taguchi ,  Kotoku Sato

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C11/4076

    摘要： An electronic instrument includes a memory device, clock lines through which complementary clock signals are transmitted to be used for synchronization of a data output operation and a data input operation for the memory device, and strobe signal lines through which a first output strobe signal, a second output strobe signal, a first input strobe signal and a second input strobe signal are transmitted to be used to settle output data from the memory device in the data output operation and to settle input data supplied to the memory device, the first and second output strobe signals being in complementary relation to each other, the first and second input strobe signals being in complementary relation to each other.

    摘要翻译： 一种电子仪器，包括：存储器件，传输互补时钟信号的时钟线，用于数据输出操作的同步和存储器件的数据输入操作;以及选通信号线，第一输出选通信号， 发送第二输出选通信号，第一输入选通信号和第二输入选通信号，以在数据输出操作中用于建立来自存储器件的输出数据，并且提供提供给存储器件的输入数据，第一和第二输出 选通信号彼此互补，第一和第二输入选通信号彼此互补。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
    半导体存储器件及其控制方法

    公开(公告)号：US20120120739A1

    公开(公告)日：2012-05-17

    申请号：US13356341

    申请日：2012-01-23

    申请人： Shinya FUJIOKA ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

    发明人： Shinya FUJIOKA ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

    IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/00

    CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

    摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

    摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。