公开(公告)号：US20060129624A1

公开(公告)日：2006-06-15

申请号：US11008848

申请日：2004-12-09

Applicant: Mohammad Abdallah ,  Maheswara Lingareddy

Inventor： Mohammad Abdallah ,  Maheswara Lingareddy

IPC: G06F7/52

CPC classification number: G06F7/535

Abstract: An apparatus and method to perform a division algorithm on an integer divisor and integer dividend. More particularly, embodiments of the invention relate to a technique to align integer operands such that a relatively fast division algorithm may be performed on the integer operands.

Abstract translation: 对整数除数和整数除数执行除法算法的装置和方法。 更具体地，本发明的实施例涉及一种对准整数操作数的技术，使得可以对整数操作数执行相对较快的分割算法。

公开(公告)号：USD435050S

公开(公告)日：2000-12-12

申请号：US101089

申请日：1999-02-25

Applicant: Brian David Wise ,  Mohammad Abdallah

Designer： Brian David Wise ,  Mohammad Abdallah

公开(公告)号：US09740612B2

公开(公告)日：2017-08-22

申请号：US13561441

申请日：2012-07-30

Applicant: Karthikeyan Avudaiyappan ,  Mohammad Abdallah

Inventor： Karthikeyan Avudaiyappan ,  Mohammad Abdallah

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/283 ,  G06F2212/608

Abstract: A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache.

公开(公告)号：US09733944B2

公开(公告)日：2017-08-15

申请号：US13879374

申请日：2011-10-12

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3804 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3848

Abstract: A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.

公开(公告)号：US09639364B2

公开(公告)日：2017-05-02

申请号：US13359832

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F12/10 ,  G06F9/355 ,  G06F12/1036 ,  G06F9/455 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0895 ,  G06F12/0897

CPC classification number: G06F9/355 ,  G06F9/30054 ,  G06F9/30174 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/4552 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1036 ,  G06F2212/604

Abstract: A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

公开(公告)号：US09274793B2

公开(公告)日：2016-03-01

申请号：US13428452

申请日：2012-03-23

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50

CPC classification number: G06F9/3836 ,  G06F9/30043 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3889 ,  G06F9/5027 ,  G06F12/0875 ,  G06F2209/507 ,  G06F2212/452 ,  Y02D10/22

Abstract: A system for executing instructions using a plurality of memory fragments for a processor. The system includes a global front end scheduler for receiving an incoming instruction sequence, wherein the global front end scheduler partitions the incoming instruction sequence into a plurality of code blocks of instructions and generates a plurality of inheritance vectors describing interdependencies between instructions of the code blocks. The system further includes a plurality of virtual cores of the processor coupled to receive code blocks allocated by the global front end scheduler, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines, wherein the code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors. A plurality memory fragments are coupled to the partitionable engines for providing data storage.

Abstract translation: 一种用于使用用于处理器的多个存储器片段来执行指令的系统。 该系统包括用于接收输入指令序列的全局前端调度器，其中全局前端调度器将输入指令序列划分为指令的多个代码块，并且生成描述代码块指令之间相互依赖关系的多个继承向量。 该系统还包括处理器的多个虚拟核心，其耦合以接收由全局前端调度器分配的代码块，其中每个虚拟核心包括多个可分区引擎的相应资源子集，其中通过使用 根据虚拟核心模式并根据各自的继承向量的可分割引擎。 多个存储器片段耦合到可分割引擎以提供数据存储。

公开(公告)号：US09207960B2

公开(公告)日：2015-12-08

申请号：US13359961

申请日：2012-01-27

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/38 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F9/30174 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/3863 ,  G06F9/4552 ,  G06F12/0875 ,  G06F2212/452

Abstract: A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest instruction using a first level conversion table. The method further includes outputting a resulting native instruction when the first level translation proceeds to completion. A second level translation of the guest instruction is performed using a second level conversion table when the first level translation does not proceed to completion, wherein the second level translation further processes the guest instruction based upon a partial translation from the first level conversion table. The resulting native instruction is output when the second level translation proceeds to completion.

Abstract translation: 一种用于翻译处理器的指令的方法。 该方法包括访问客户指令并使用第一级转换表执行访客指令的第一级转换。 该方法还包括当第一级转换进行到完成时输出结果本地指令。 当第一级转换不进行到完成时，使用第二级转换表执行访客指令的第二级转换，其中第二级转换还基于来自第一级转换表的部分转换进一步处理客户指令。 当第二级转换进行到完成时，输出所产生的本机指令。

公开(公告)号：US20150248294A1

公开(公告)日：2015-09-03

申请号：US14376825

申请日：2011-10-21

Applicant: Mandeep Singh ,  Mohammad Abdallah

Inventor： Mandeep Singh ,  Mohammad Abdallah

IPC: G06F9/30 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F9/30043 ,  G06F9/34 ,  G06F9/3834 ,  G06F12/0888 ,  G06F13/1642 ,  G06F2212/6046

Abstract: Fast unaligned memory access. In accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.

Abstract translation: 快速对齐内存访问。 根据本发明的第一实施例，计算设备包括被配置为对加载操作进行排队的加载队列存储器结构以及被配置为排队存储操作的存储队列存储器结构。 计算设备还包括至少一个比特，其被配置为指示存在用于所述加载队列存储器结构的条目的未对齐地址组件，并且至少一个比特被配置为指示存在用于所述 存储队列内存结构。 加载队列存储器还可以包括被配置为指示从所述存储队列存储器结构到所述加载队列存储器结构的未对齐地址组件的数据转发的存储器。

公开(公告)号：US20150186144A1

公开(公告)日：2015-07-02

申请号：US14360284

申请日：2011-11-22

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3017 ,  G06F9/3808 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3887

Abstract: A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The plurality of dependent code groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

Abstract translation: 一种用于加速微处理器的代码优化的方法。 该方法包括使用指令获取组件获取传入的微指令序列，并将获取的宏指令传送到解码组件以解码为微指令。 通过将微指令序列重排序到包括多个相关代码组的优化微指令序列中来执行优化处理。 然后将多个相关代码组输出到微处理器的多个引擎并行执行。 优化的微指令序列的副本被存储到序列高速缓存中，用于随后的命中优化微指令序列的使用。

公开(公告)号：US08342076B2

公开(公告)日：2013-01-01

申请号：US12341221

申请日：2008-12-22

Applicant: Christopher J. Prager ,  Gary R. Sprague ,  Mohammad Abdallah

Inventor： Christopher J. Prager ,  Gary R. Sprague ,  Mohammad Abdallah

IPC: B60T17/08 ,  B60T17/00

CPC classification number: B60T17/083

Abstract: An improved diaphragm-type pneumatic brake actuator includes a flange case, a cover cooperable with the flange case, a flexible diaphragm extending between the flange case and the cover forming a lower pneumatic chamber and an upper pneumatic chamber on opposed sides of the diaphragm. A piston assembly is disposed in the cover for moving a spring between compressed and decompressed positions. A spring guide is disposed between the cover and the piston assembly in the upper chamber. The spring guide prevents direct contact of the spring with the cover to prevent formation of a corrosion cell.

Abstract translation: 改进的隔膜式气动制动器致动器包括凸缘壳体，与凸缘壳体配合的盖子，在凸缘壳体和盖子之间延伸的柔性隔膜，形成下气动室和在隔膜的相对侧上的上气动室。 活塞组件设置在盖中，用于在压缩位置和减压位置之间移动弹簧。 弹簧引导件设置在上室中的盖和活塞组件之间。 弹簧导向器防止弹簧与盖子的直接接触，以防止形成腐蚀电池。