公开(公告)号：US20170115352A1

公开(公告)日：2017-04-27

申请号：US15336676

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Dheepakkumaran Jayaraman ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Sailendra Chadalavda ,  Jonathon E. Colburn ,  Kevin Wilder ,  Mahmut Yilmaz

IPC: G01R31/317 ,  G01R31/3177

Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

公开(公告)号：US20170115346A1

公开(公告)日：2017-04-27

申请号：US15336747

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Rajendra Kumar reddy.S ,  Bala Tarun Nelapatla ,  Sailendra Chadalavda ,  Shantanu Sarangi

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/2607 ,  G01R31/2803 ,  G01R31/2806 ,  G01R31/2834 ,  G01R31/31701 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318555 ,  G01R31/318572 ,  G06F11/00

Abstract: A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.

公开(公告)号：US20240419568A1

公开(公告)日：2024-12-19

申请号：US18815553

申请日：2024-08-26

Applicant: NVIDIA Corporation

Inventor： Jonah Alben ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

IPC: G06F11/267 ,  G06F1/3296 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273

Abstract: In various examples, one or more components or regions of a processing unit-such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

公开(公告)号：US11726139B2

公开(公告)日：2023-08-15

申请号：US17883199

申请日：2022-08-08

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G06F11/14 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G01R31/3181 ,  G06F11/267 ,  G01R31/3185 ,  G06F11/273

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/3187 ,  G01R31/31813 ,  G01R31/318555 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/2273 ,  G06F11/267 ,  G06F11/27 ,  G06F11/273 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US10451676B2

公开(公告)日：2019-10-22

申请号：US15336736

申请日：2016-10-27

Applicant: NVIDIA Corporation

Inventor： Milind Sonawane ,  Amit Sanghani ,  Shantanu Sarangi ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Sailendra Chadalavda ,  Rajendra Kumar Reddy.S ,  Mahmut Yilmaz ,  Pavan Kumar Datla Jagannadha

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00

Abstract: A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.

公开(公告)号：US20190195947A1

公开(公告)日：2019-06-27

申请号：US16230929

申请日：2018-12-21

Applicant: Nvidia Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3177 ,  G01R31/3181 ,  G06F11/36 ,  G06F11/27 ,  G06F11/22 ,  G06F11/14

CPC classification number: G01R31/31724 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/3187 ,  G06F11/1417 ,  G06F11/2268 ,  G06F11/27 ,  G06F11/3688

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US10317463B2

公开(公告)日：2019-06-11

申请号：US15336747

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Rajendra Kumar reddy.S ,  Bala Tarun Nelapatla ,  Sailendra Chadalavda ,  Shantanu Sarangi

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00

Abstract: A method for testing. The method includes sending a single instruction over a JTAG interface to a JTAG controller to select a first internal test data register of a plurality of data registers. The method includes programming the first internal test data register using the JTAG interface to configure mode control access and state control access for a test controller implementing a sequential scan architecture to test a chip at a system level.

公开(公告)号：US20170115351A1

公开(公告)日：2017-04-27

申请号：US15336626

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Pavan Kumar Datla Jagannadha ,  Dheepakkumaran Jayaraman ,  Anubhav Sinha ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Mahmut Yilmaz

IPC: G01R31/317 ,  G01R31/3177

Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

公开(公告)号：US20170115345A1

公开(公告)日：2017-04-27

申请号：US15336736

申请日：2016-10-27

Applicant: NVIDIA Corporation

Inventor： Milind Sonawane ,  Amit Sanghani ,  Shantanu Sarangi ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Sailendra Chadalavda ,  Rajendra Kumar reddy.S ,  Mahmut Yilmaz

IPC: G01R31/3177 ,  G01R31/317

Abstract: A method for testing. An external clock frequency is generated. Test data is supplied over a plurality of SSI connections clocked at the external clock frequency, wherein the test data is designed for testing a logic block. A DSTA module is configured for the logic block that is integrated within a chip to a bandwidth ratio, wherein the bandwidth ratio defines the plurality of SSI connections and a plurality of PSI connections of the chip. The external clock frequency is divided down using the bandwidth ratio to generate an internal clock frequency, wherein the bandwidth ratio defines the external clock frequency and the internal clock frequency. The test data is scanned over the plurality of PSI connections clocked at the internal clock frequency according to the bandwidth ratio, wherein the plurality of PSI connections is configured for inputting the test data to the plurality of scan chains.

公开(公告)号：US12291219B2

公开(公告)日：2025-05-06

申请号：US18048952

申请日：2022-10-24

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02 ,  B60W50/00

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.