中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

62 records (took 0.031 seconds)

    Non-volatile semiconductor memory device
    21.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US5898614A

    公开(公告)日：1999-04-27

    申请号：US861033

    申请日：1997-05-21

    Applicant: Nobuyoshi Takeuchi

    Inventor： Nobuyoshi Takeuchi

    IPC: G11C11/56 ,  H01L27/115 ,  G11C7/00

    CPC classification number: G11C11/5642 ,  G11C11/5621 ,  H01L27/115 ,  G11C2211/5634

    Abstract: A non-volatile semiconductor memory device comprises a plurality of memory cells each including a semiconductor substrate of a first conductivity type having a main surface region, a control gate portion formed in said main surface region of the semiconductor substrate and consisting of an impurity diffusion region of a second conductivity type opposite to said first conductivity type, a reading transistor portion formed on the main surface region of the substrate and consisting of a MOS type transistor structure, and a floating gate portion formed over the control gate portion and the reading transistor portion. These memory cells differ from each other in an overlapping area ratio Ap/An, where An denotes an area of an over-lapping portion between the floating gate and the impurity diffusion region of the control gate portion, Ap represents an area of an overlapping portion between the floating gate and an active region of the reading transistor portion.

    Abstract translation: 非易失性半导体存储器件包括多个存储单元，每个存储单元包括具有主表面区域的第一导电类型的半导体衬底，形成在半导体衬底的所述主表面区域中的控制栅极部分，由杂质扩散区域 与所述第一导电类型相反的第二导电类型，形成在所述衬底的所述主表面区域上并由MOS型晶体管结构组成的读取晶体管部分，以及形成在所述控制栅极部分和所述读取晶体管部分上的浮动栅极部分 。 这些存储单元以重叠面积比Ap / An彼此不同，其中An表示浮动栅极和控制栅极部分的杂质扩散区域之间的重叠部分的面积，Ap表示重叠部分的面积 在浮置栅极和读取晶体管部分的有源区域之间。

    Nonvolatile memory device with verify function
    22.
    发明授权
    Nonvolatile memory device with verify function 失效
    具有验证功能的非易失性存储器件

    公开(公告)号：US5886927A

    公开(公告)日：1999-03-23

    申请号：US11450

    申请日：1998-07-09

    Applicant: Nobuyoshi Takeuchi

    Inventor： Nobuyoshi Takeuchi

    IPC: G11C16/34 ,  G11C16/06

    CPC classification number: G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    Abstract: One verify cell is connected to one word line, together with a plurality of array cells, and has a threshold value almost the same as the array cells. A write voltage or an erase voltage is applied to the array cells, setting the voltage applied to the verify cell at a small value, thereby electrically changing the threshold value of the verify cell. Alternatively, the sense ratio of a sense amplifier is changed with respect to the output of the verify cell and the output of a reference cell, thereby electrically changing the apparent threshold value of the verify cell. Data is thereby written into or erased from the array cells earlier than into or from the verify cell. Hence, the verification of the memory cells is accomplished by when the verify cell is verified.

    Abstract translation: PCT No.PCT / JP97 / 02006 Sec。 371日期：1998年7月9日 102（e）日期1998年7月9日PCT 1997年6月11日提交一个验证单元与多个阵列单元一起连接到一个字线，并且具有与阵列单元几乎相同的阈值。 将写入电压或擦除电压施加到阵列单元，将施加到验证单元的电压设置为较小的值，由此电气改变验证单元的阈值。 或者，感测放大器的感测比相对于验证单元的输出和参考单元的输出而改变，从而电气地改变验证单元的表观阈值。 因此，数据在编码单元之前或之后从阵列单元写入或擦除。 因此，当验证单元被验证时，可以实现对存储器单元的验证。

    Phosphorescent phosphor
    23.
    发明授权
    Phosphorescent phosphor 失效
    磷光荧光粉

    公开(公告)号：US5686022A

    公开(公告)日：1997-11-11

    申请号：US544810

    申请日：1995-10-18

    Applicant: Yoshihiko Murayama ,  Nobuyoshi Takeuchi ,  Yasumitsu Aoki ,  Takashi Matsuzawa

    Inventor： Yoshihiko Murayama ,  Nobuyoshi Takeuchi ,  Yasumitsu Aoki ,  Takashi Matsuzawa

    IPC: C09K11/64 ,  C09K11/02 ,  C09K11/77 ,  C09K11/80

    CPC classification number: C09K11/02 ,  C09K11/7734 ,  C09K11/7792

    Abstract: A phosphorescent phosphor comprising a matrix expressed by M.sub.1-x Al.sub.2 O.sub.4-x (except X=0) in which M is at least one metal element selected from a group consisting of calcium, strontium and barium. X is in a range -0.33.ltoreq..times..ltoreq.0.60 (except x=0). Europium is doped to said matrix as an activator and at least one element selected from a group consisting of lanthanum, cerium, praseodymium, neodymium, samarium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium and lutetium is doped to said matrix as a co-activator. Magnesium is doped to M.

    Abstract translation: 一种磷光体荧光体，其包含由M1-xAl2O4-x（X = 0除外）表示的基质，其中M为选自钙，锶和钡中的至少一种金属元素。 X在-0.33

    Non-volatile semiconductor memory device and method of manufacturing the same
    24.
    发明授权
    Non-volatile semiconductor memory device and method of manufacturing the same 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US5661056A

    公开(公告)日：1997-08-26

    申请号：US533169

    申请日：1995-09-25

    Applicant: Nobuyoshi Takeuchi

    Inventor： Nobuyoshi Takeuchi

    IPC: H01L21/28 ,  H01L21/318 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L21/28202 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/518 ,  Y10S438/954

    Abstract: A tunnel oxide film is formed on the surface of a p-type silicon substrate, and a floating gate electrode made from a polysilicon film is formed on the surface of the tunnel oxide film. On the surface of the floating gate electrode, a control gate electrode is formed via an NON film formed by sequentially stacking a silicon nitride film, a silicon oxide film, and a silicon nitride film. A side oxide film is formed on the side surfaces of the floating gate electrode and the control gate electrode. Source and drain regions made from an n-type diffused layer are formed on the surfaces of element regions of the silicon substrate on the two sides of the floating gate electrodes.

    Abstract translation: 隧道氧化膜形成在p型硅衬底的表面上，并且在隧道氧化膜的表面上形成由多晶硅膜制成的浮栅。 在浮栅电极的表面上，通过依次层叠氮化硅膜，氧化硅膜和氮化硅膜而形成的NON膜来形成控制栅电极。 在浮栅电极和控制栅电极的侧表面上形成侧氧化膜。 源极和漏极区由n型扩散层形成在浮动栅电极两侧的硅衬底的元件区域的表面上。

    Information reading method
    25.
    发明授权
    Information reading method 失效
    信息阅读方法

    公开(公告)号：US5220166A

    公开(公告)日：1993-06-15

    申请号：US756552

    申请日：1991-09-09

    Applicant: Nobuyoshi Takeuchi ,  Yuzo Ishikawa ,  Kaori Kanesaka

    Inventor： Nobuyoshi Takeuchi ,  Yuzo Ishikawa ,  Kaori Kanesaka

    IPC: G06K7/12

    CPC classification number: G06K7/12

    Abstract: An information reading method includes the steps of irradiating a phosphor activated by neodymium and ytterbium ions with exciting light of a wavelength between 500 nm and 780 nm that can excite the neodymium ions, and reading the information by receiving the light emitted from the phosphor with a photodetector designed to detect light with wavelengths between 840 m and 1100 nm. Consequently, the information recorded using the phosphor activated by neodymium and ytterbium ions can be read with a high performance without using a filter for cutting the exciting light.

    Abstract translation: 信息读取方法包括以下步骤：用能够激发钕离子的波长为500nm至780nm的激发光照射由钕和镱离子激活的荧光体，并且通过接收从荧光体发射的光来读取信息 光电检测器设计用于检测波长在840米和1100纳米之间的光。 因此，使用由钕和镱离子激活的荧光体记录的信息可以以高性能读取，而不使用用于切割激发光的滤光器。

    LAMP
    26.
    发明申请
    LAMP 有权
    灯

    公开(公告)号：US20140152177A1

    公开(公告)日：2014-06-05

    申请号：US14234187

    申请日：2012-02-03

    Applicant: Tsugihiro Matsuda ,  Nobuyoshi Takeuchi ,  Yoshinori Kakuno ,  Masahiro Miki ,  Hideo Nagai ,  Takaari Uemoto

    Inventor： Tsugihiro Matsuda ,  Nobuyoshi Takeuchi ,  Yoshinori Kakuno ,  Masahiro Miki ,  Hideo Nagai ,  Takaari Uemoto

    IPC: F21K99/00

    CPC classification number: F21K9/1355 ,  F21K9/23 ,  F21K9/232 ,  F21K9/238 ,  F21K9/90 ,  F21V19/003 ,  F21V23/006 ,  F21V29/15 ,  F21V29/507 ,  F21Y2115/10

    Abstract: In a lamp: an LED module and a circuit unit for lighting are housed within an envelope composed of a globe and a case; the LED module is attached to an end of an extension member that extends from a mount, which closes an opening at one end of the case, into the globe; the circuit unit is mounted inside the case; an insulation member disposed inside the case ensures insulation between the mount, which is made of metal, and the circuit unit; the insulation member has a bottomed cylinder portion inserted into the mount, and a protrusion portion formed on an outer circumference of the based cylinder portion that protrudes toward an inner surface of the mount; and the insulation member is attached to the mount by the protrusion portion pressing against the inner surface of the mount.

    Abstract translation: 在灯中：用于照明的LED模块和电路单元容纳在由球体和壳体组成的信封内; LED模块附接到延伸构件的端部，该延伸构件从将壳体的一端封闭开口的安装件延伸到球体中; 电路单元安装在壳体内; 设置在壳体内的绝缘构件确保由金属制成的安装座与电路单元之间的绝缘; 所述绝缘构件具有插入所述安装件中的有底圆筒部分，以及形成在所述基座筒部的外周上朝向所述安装件的内表面突出的突出部分; 并且所述绝缘构件通过所述突出部分抵靠所述安装件的内表面附接到所述安装件。

Patent Agency Ranking