公开(公告)号：US10922267B2

公开(公告)日：2021-02-16

申请号：US14718432

申请日：2015-05-21

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary J. Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Vitaly Kalashnikov ,  Sitij Agrawal

IPC: G06F15/80 ,  G06F9/30 ,  G06F15/78 ,  G06F9/38 ,  G06F17/14

Abstract: A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more graphics processing instructions. The computer processor may be implemented as a monolithic integrated circuit.

公开(公告)号：US20180203806A1

公开(公告)日：2018-07-19

申请号：US15868513

申请日：2018-01-11

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  A. Joseph Hoane ,  Lei Wang ,  Gary Nacer ,  Aaron G. Milbury ,  Enrique A. Barria ,  Paul Hurtley

IPC: G06F12/1027 ,  G06F12/1009

Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

公开(公告)号：US20180173527A1

公开(公告)日：2018-06-21

申请号：US15841959

申请日：2017-12-14

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola ,  Vaidyanathan Thevangudi Ramadurai

IPC: G06F9/30

Abstract: A processor including a first storage to store a first data item, a second storage, and an execution unit comprising a logic circuit encoding an instruction, the instruction comprising a first field to store an identifier of the first storage, a second field to store an identifier of the second storage, and a third field to store an identifier representing a rounding rule, wherein the execution unit is to execute the instruction to generate a second data item based on the first data item, round the second data item according to the rounding rule specified by the instruction, and store the rounded second data item in the second storage.

公开(公告)号：US20160364236A1

公开(公告)日：2016-12-15

申请号：US15155570

申请日：2016-05-16

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan

IPC: G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/462

Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.

Abstract translation: 计算机处理器可以包括多个硬件线程。 计算机处理器还可以包括用于硬件线程的状态的状态处理器逻辑。 状态处理器逻辑可以包括每个线程逻辑，其包含在多个硬件线程的每个硬件线程中被复制的状态和独立于多个硬件线程中的每个硬件线程的公共逻辑。 计算机处理器还可以包括单线程模式逻辑，以仅从多个硬件线程中的一个硬件线程以单线程模式执行指令。 计算机处理器还可以包括第二模式逻辑，用于同时执行来自多个硬件线程的多于一个硬件线程的第二模式的指令。 计算机处理器还可以包括在第一模式和第二模式之间切换的巫师模式逻辑。

公开(公告)号：US20160313996A1

公开(公告)日：2016-10-27

申请号：US15086711

申请日：2016-03-31

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

IPC: G06F9/30 ,  G06F3/06

Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.

Abstract translation: 公开了一种具有地址寄存器文件的计算机处理器。 计算机处理器可以包括存储器。 计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。 计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。 计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。 处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及 添加在指令中编码的位移值。

公开(公告)号：US20160313995A1

公开(公告)日：2016-10-27

申请号：US15086752

申请日：2016-03-31

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3013 ,  G06F9/322 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/6028 ,  G06F2212/651 ,  G06F2212/684

Abstract: A computer processor with indirect only branching is disclosed. The computer processor may include one or more target registers. The computer processor may include processing logic in signal communication with the one or more target registers. The processing logic may execute a non-interrupting branch instruction based on a value stored in a target register of the one or more target registers. The non-interrupting branch instruction may use the one or more target registers to specify a destination address of a branch specified by the non-interrupting branch instruction.

Abstract translation: 公开了一种仅间接分支的计算机处理器。 计算机处理器可以包括一个或多个目标寄存器。 计算机处理器可以包括与一个或多个目标寄存器进行信号通信的处理逻辑。 处理逻辑可以基于存储在一个或多个目标寄存器的目标寄存器中的值来执行非中断分支指令。 非中断分支指令可以使用一个或多个目标寄存器来指定由非中断分支指令指定的分支的目的地地址。

公开(公告)号：US11544214B2

公开(公告)日：2023-01-03

申请号：US14709730

申请日：2015-05-12

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary J. Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola ,  Vitaly Kalashnikov ,  Sitij Agrawal

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F17/14 ,  G06F9/46 ,  G06F15/78

Abstract: A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.

公开(公告)号：US10908909B2

公开(公告)日：2021-02-02

申请号：US15155570

申请日：2016-05-16

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/455

Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.

公开(公告)号：US10514915B2

公开(公告)日：2019-12-24

申请号：US15086711

申请日：2016-03-31

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary Nacer ,  C. John Glossner ,  A. Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F9/32 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/1027 ,  G06F3/06

Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.

公开(公告)号：US10339095B2

公开(公告)日：2019-07-02

申请号：US14716285

申请日：2015-05-19

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： Mayan Moudgill ,  Gary J. Nacer ,  C. John Glossner ,  Arthur Joseph Hoane ,  Paul Hurtley ,  Murugappan Senthilvelan ,  Pablo Balzola ,  Vitaly Kalashnikov ,  Sitij Agrawal

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/38 ,  G06F17/14 ,  G06F15/78

Abstract: A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor further comprises processing logic configured to operate on the varying number of elements in the vector register file using one or more digital signal processing instructions. The computer processor may be implemented as a monolithic integrated circuit.