公开(公告)号：US20170075397A1

公开(公告)日：2017-03-16

申请号：US14852941

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Mehdi Saeidi ,  Arpit Mittal ,  Farsheed Mahmoudi ,  Rajat Mittal

IPC: G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/16

Abstract: A method includes: generating a power consumption reading indicative of power consumption of a device, comparing the power consumption reading to a power threshold, wherein the power threshold represents a level of power consumption corresponding to a rise in temperature of an exterior surface of the device; in response to determining that the power consumption reading exceeds the power threshold, measuring cumulative power consumption over time from the power consumption reading; comparing the cumulative power consumption over time to an energy threshold, wherein the energy threshold corresponds to a temperature threshold for the exterior surface of the device; and in response to determining that the cumulative power consumption over time exceeds the energy threshold, reducing an operating parameter of the device to reduce power consumption.

Abstract translation: 一种方法包括：产生指示设备的功耗的功率消耗读数，将功耗读取与功率阈值进行比较，其中功率阈值表示与设备的外表面的温度升高相对应的功耗水平 ; 响应于确定所述功耗读数超过所述功率阈值，从所述功耗读数测量随时间的累积功耗; 将随时间的累积功耗与能量阈值进行比较，其中所述能量阈值对应于所述装置的外表面的温度阈值; 并且响应于确定随着时间的累积功率消耗超过能量阈值，减少设备的操作参数以降低功耗。

公开(公告)号：US20160179181A1

公开(公告)日：2016-06-23

申请号：US14579899

申请日：2014-12-22

Applicant: QUALCOMM INCORPORATED

Inventor： James Thomas Doyle ,  Zhengming Fu ,  Farsheed Mahmoudi ,  Amirali Shayan Arani ,  Nazanin Darbanian

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G05F1/575 ,  G06F1/3296 ,  H02M2001/0045 ,  H02M2003/1566

Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply connects a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. Integration of the voltage regulator on the SoC reduces parasitic impedance be between the voltage regulator and the load to aid in reducing voltage droops. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.

Abstract translation: 诸如移动电话等复杂设备的片上系统芯片（SoC）集成电路的运行模式变化会导致电流需求的尖峰，从而导致电压下降，从而破坏了SoC的运行。 混合并联电源并联连接开关电源和低压差稳压器，以提供高效率和快速的响应时间。 电压调节器在SoC上的集成可减少电压调节器和负载之间的寄生阻抗，有助于降低电压下降。 开关电源和低压差稳压器可以将其输出调节为稍微不同的电压电平。 这可以允许开关电源供应大部分SoC的当前需求。

公开(公告)号：US20160118895A1

公开(公告)日：2016-04-28

申请号：US14863269

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Farsheed Mahmoudi ,  James Thomas Doyle ,  Chuang Zhang ,  Zhengming Fu

IPC: H02M3/158 ,  G06F1/32

CPC classification number: H02M3/1584 ,  G06F1/3296 ,  H02M1/088 ,  H02M3/157 ,  H02M2001/0048 ,  H02M2001/0054 ,  Y02B70/1491

Abstract: An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter.

Abstract translation: 公开了一种用于在具有同步降压转换器的反馈回路中提供有效操作的装置和方法。 同步降压转换器包括多个单独可选择的相位，其中每个相位具有多个可单独选择和并联的开关支路。 电路存储将多个不同负载值与各自配置设置相关联的信息，每个配置设置定义多个相位和多个开关支路。 当负载变化时，电路测量负载并选择适当的配置设置。 该电路应用所选配置设置来操作降压转换器中的相数和多个并联开关支路。

公开(公告)号：US20160118887A1

公开(公告)日：2016-04-28

申请号：US14630362

申请日：2015-02-24

Applicant: QUALCOMM Incorporated

Inventor： Chuang Zhang ,  James Thomas Doyle ,  Farsheed Mahmoudi ,  Amirali Shayan Arani

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M1/126 ,  H02M3/07 ,  H02M7/483 ,  H02M2003/072

Abstract: A circuit including: a control system for a three-level buck converter, the three-level buck converter including multiple input switches, each of the input switches receiving one of a plurality of different pulse width modulated signals, the control system including: a first clock signal and a second clock signal, the second clock signal being a phase-shifted version of the first clock signal; ramp generating circuitry receiving the first and second clock signals and producing first and second ramp signals, respectively, from the first and second clock signals; a first comparing circuit receiving the first ramp signal and producing a first one of the pulse width modulated signals therefrom; and a second comparing circuit receiving the second ramp signal and producing a second one of the pulse width modulated signals therefrom.

Abstract translation: 一种电路，包括：用于三电平降压转换器的控制系统，所述三电平降压转换器包括多个输入开关，每个输入开关接收多个不同的脉宽调制信号中的一个，所述控制系统包括：第一 时钟信号和第二时钟信号，所述第二时钟信号是所述第一时钟信号的相移版本; 斜坡发生电路接收第一和第二时钟信号并分别从第一和第二时钟信号产生第一和第二斜坡信号; 接收所述第一斜坡信号并从其产生所述脉冲宽度调制信号中的第一个信号的第一比较电路; 以及第二比较电路，接收所述第二斜坡信号并从其产生所述脉冲宽度调制信号中的第二个。

公开(公告)号：US20140253279A1

公开(公告)日：2014-09-11

申请号：US13791113

申请日：2013-03-08

Applicant: QUALCOMM INCORPORATED

Inventor： James Thomas Doyle ,  Amirali Shayan Arani ,  Farsheed Mahmoudi

IPC: H01F27/36

CPC classification number: H01F27/365 ,  H01F17/02 ,  H01F17/03 ,  H01F27/292 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/19106

Abstract: Some implementations provide a coupled inductor structure that includes a first discrete inductor configured to generate a magnetic field, a second discrete inductor, and a first ferromagnetic layer coupled to the first discrete inductor and the second discrete inductor. The first ferromagnetic layer is configured to concentrate the magnetic field generated by the first discrete inductor within the coupled inductor structure. In some implementations, the coupled inductor structure further includes a second ferromagnetic layer coupled to the first discrete inductor and the second discrete inductor. The second ferromagnetic layer is configured to concentrate the magnetic field generated by the first discrete inductor within the coupled inductor structure. In some implementations, the coupled inductor structure is a bifilar inductor structure. The first discrete inductor includes a first set of windings and the second discrete inductor includes a second set of windings. The first and second discrete inductors share a common core.

Abstract translation: 一些实施方案提供耦合电感器结构，其包括被配置为产生磁场的第一离散电感器，第二离散电感器和耦合到第一分立电感器和第二分立电感器的第一铁磁层。 第一铁磁层被配置为将由第一离散电感器产生的磁场集中在耦合的电感器结构内。 在一些实施方案中，耦合电感器结构还包括耦合到第一分立电感器和第二分立电感器的第二铁磁层。 第二铁磁层被配置为将由第一离散电感器产生的磁场集中在耦合的电感器结构内。 在一些实施方案中，耦合电感器结构是双电感器结构。 第一离散电感器包括第一组绕组，第二分立电感器包括第二组绕组。 第一和第二离散电感共享共同的核心。

公开(公告)号：US20140225706A1

公开(公告)日：2014-08-14

申请号：US13794558

申请日：2013-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： James Thomas Doyle ,  Farsheed Mahmoudi ,  Amirali Shayan Arani

IPC: H01F5/00 ,  H01F41/02

CPC classification number: H01F41/02 ,  H01F17/0006 ,  H01F27/2871 ,  H01F2017/004 ,  H01L23/645 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1433 ,  H01L2924/15313 ,  H01L2924/15331 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/19106 ,  Y10T29/49071 ,  H01L2924/00

Abstract: Some novel features pertain to an in-substrate inductor structure that includes a first inductor winding, a second inductor winding and a substrate. The first inductor winding includes an electrically conductive material. The second inductor winding includes an electrically conductive material. The substrate is laterally located between the first inductor winding and the second inductor winding. The substrate is configured to provide structural coupling of the first and second inductor windings. In some implementations, the first inductor winding is laterally co-planar to the second inductor winding. In some implementations, the first inductor winding has a first spiral shape and the second inductor winding has a second spiral shape. In some implementations, the first inductor winding and the second inductor winding have an elongated circular shape. In some implementations, the substrate is a silicon substrate.

Abstract translation: 一些新颖的特征涉及内置电感器结构，其包括第一电感器绕组，第二电感器绕组和衬底。 第一电感器绕组包括导电材料。 第二电感线圈包括导电材料。 衬底横向位于第一电感器绕组和第二电感器绕组之间。 衬底被配置为提供第一和第二电感器绕组的结构耦合。 在一些实施方案中，第一电感器绕组与第二电感器绕组横向共面。 在一些实施方案中，第一电感器绕组具有第一螺旋形状并且第二电感器绕组具有第二螺旋形状。 在一些实施方案中，第一电感器绕组和第二电感器绕组具有细长的圆形形状。 在一些实施方式中，衬底是硅衬底。