公开(公告)号：US20160307620A1

公开(公告)日：2016-10-20

申请号：US14690204

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Yanru Li

IPC: G11C11/406 ,  G11C29/42 ,  G11C29/36 ,  G11C11/4096

CPC classification number: G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract translation: 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

公开(公告)号：US20160276009A1

公开(公告)日：2016-09-22

申请号：US14818809

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

IPC: G11C11/16 ,  G11C29/44

CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

公开(公告)号：US09406354B1

公开(公告)日：2016-08-02

申请号：US14693755

申请日：2015-04-22

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/08 ,  G11C7/067 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/22 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/26

Abstract: A read circuit for a memory cell may include an integrated logic circuit for sensing a current change. The integrated logic sensing circuit may be an offset cancelling single ended integrated logic sensing circuit. The circuit may include an offset canceling single ended sensing circuit coupled to a supply voltage, an offset canceling single ended sense amplifier circuit having a sense amplifier input coupled to the offset canceling single ended sensing circuit and a sense amplifier output, and a cell array coupled to a sensing circuit output and a ground.

Abstract translation: 用于存储单元的读取电路可以包括用于感测电流变化的集成逻辑电路。 集成逻辑感测电路可以是偏移消除单端集成逻辑感测电路。 电路可以包括耦合到电源电压的偏移消除单端感测电路，具有耦合到偏移消除单端感测电路的读出放大器输入和读出放大器输出的偏移消除单端读出放大器电路，以及耦合到 到感测电路输出和地。

公开(公告)号：US09378793B2

公开(公告)日：2016-06-28

申请号：US13721092

申请日：2012-12-20

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Jungwon Suh

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/16 ,  G11C11/1653 ,  G11C2211/5643 ,  Y10T29/49117

Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

Abstract translation: 用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。 集成电路包括处理器，其中没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或 多个包装。 第二包还包括存储器控制器逻辑。 简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主内存之间的积极预取，改进的页面处理和改进的密封能力。

公开(公告)号：US09378081B2

公开(公告)日：2016-06-28

申请号：US14146628

申请日：2014-01-02

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Mosaddiq Saifuddin

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G06F12/00 ,  G06F13/16

CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G06F2201/88

Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

Abstract translation: 一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。 该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。 第一个地址对应于存储器阵列的第一个元素。 第二地址对应于包括在控制器内的存储器上的第二元件。 响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。

公开(公告)号：US20160125953A1

公开(公告)日：2016-05-05

申请号：US14994231

申请日：2016-01-13

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract translation: 一次性编程（OTP）装置单元包括具有反向连接的磁隧道结（MTJ），用于在编程期间将MTJ置于反并联电阻状态。 在其反并联电阻状态下增加的MTJ电阻会导致更高的编程电压，从而减少编程时间和编程电流。

公开(公告)号：US09183082B2

公开(公告)日：2015-11-10

申请号：US13752419

申请日：2013-01-29

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

IPC: G06F7/02 ,  G06F11/10 ,  G11C17/02 ,  G11C17/14 ,  G11C17/18 ,  G11C29/02 ,  G11C29/44

CPC classification number: G06F11/1048 ,  G11C11/16 ,  G11C17/02 ,  G11C17/146 ,  G11C17/18 ,  G11C29/027 ,  G11C2029/4402

Abstract: A circuit includes a first one-time programmable (OTP) element and a second OTP element. The circuit also includes error detection circuitry coupled to receive a first representation of data from the first OTP element. The circuit further includes output circuitry responsive to an output of the error detection circuitry to output an OTP read result based on the first representation of the data or based on a second representation of the data from the second OTP element.

Abstract translation: 电路包括第一个一次性可编程（OTP）元件和第二个OTP元件。 电路还包括耦合以从第一OTP元件接收数据的第一表示的错误检测电路。 电路还包括响应于错误检测电路的输出的输出电路，以基于数据的第一表示或基于来自第二OTP元件的数据的第二表示来输出OTP读取结果。

公开(公告)号：US20150318057A1

公开(公告)日：2015-11-05

申请号：US14266326

申请日：2014-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Xiangyu Dong

IPC: G11C29/02 ,  G11C29/30 ,  G11C7/10 ,  G11C16/26 ,  G11C16/30 ,  G11C14/00 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C29/026 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/16 ,  G11C11/1673 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  G11C16/26 ,  G11C16/30 ,  G11C29/30 ,  G11C29/52 ,  G11C2029/0411

Abstract: A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.

Abstract translation: 一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。 感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。 选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并且使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。 第二感测延迟比第一感测延迟更长。

公开(公告)号：US09164729B2

公开(公告)日：2015-10-20

申请号：US13759130

申请日：2013-02-05

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Peiyuan Wang ,  Raghu Sagar Madala ,  Senthil Kumar Govindaswamy ,  Kendrick H. Yuen ,  Robert P. Gilmore ,  Jung Pill Kim ,  Seung H. Kang

IPC: G06F7/58

CPC classification number: G06F7/58 ,  G06F7/588

Abstract: A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue.

Abstract translation: 一种用于通过检测物理熵源是处于状态A还是处于状态B从具有状态A和状态B的物理熵源生成随机二进制序列的方法和装置，试图移动物理熵源的状态 以小于100％确定性的概率方式处于相反状态，并且在尝试移位之前基于检测到的状态和物理熵源的状态产生四个输出中的一个。 将输出放置在第一和第二队列中，并从每个队列成对提取。 基于从每个队列提取的序列输出随机二进制位。

公开(公告)号：US20150186198A1

公开(公告)日：2015-07-02

申请号：US14146628

申请日：2014-01-02

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Mosaddiq Saifuddin

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/076 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/16 ,  G06F13/1668 ,  G06F2201/88

Abstract: A method includes storing, at a counter, a first value indicating a count of read operations in which a bit error is detected in data associated with a first address. The method further includes, in response to the first value exceeding a first threshold value, remapping the first address to a second address using a controller that is coupled to a memory array. The first address corresponds to a first element of the memory array. The second address corresponds to a second element that is included at a memory within the controller. Remapping the first address includes, in response to receiving a first read request for data located at the first address, replacing a first value read from the first element with a second value read from the second element.

Abstract translation: 一种方法包括在计数器处存储指示在与第一地址相关联的数据中检测到位错误的读取操作的计数的第一值。 该方法还包括响应于第一值超过第一阈值，使用耦合到存储器阵列的控制器将第一地址重新映射到第二地址。 第一个地址对应于存储器阵列的第一个元素。 第二地址对应于包括在控制器内的存储器上的第二元件。 响应于接收到位于第一地址的数据的第一读取请求，重映射第一地址包括用从第二元素读取的第二值替换从第一元素读取的第一值。