公开(公告)号：US20210351276A1

公开(公告)日：2021-11-11

申请号：US16868376

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Peijie FENG ,  Chenjie TANG

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

公开(公告)号：US20200020795A1

公开(公告)日：2020-01-16

申请号：US16033597

申请日：2018-07-12

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Ye LU ,  Haining YANG ,  Hyeokjin LIM

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/321

Abstract: A semiconductor device includes a substrate, a gate region formed on the substrate, a self-aligned gate cut formed in the gate region, and a middle of line (MOL) area formed on the gate region, wherein the self-aligned gate cut provides critical dimensions in a range from 5 nm to 30 nm. The self-aligned gate cut reduces capacitance and power, provides flexibility in placement of the MOL area, and reduces local routing congestion.

公开(公告)号：US20200020686A1

公开(公告)日：2020-01-16

申请号：US16035387

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Yan WANG ,  Jie DENG ,  Giridhar NALLAPATI

IPC: H01L27/08 ,  H01L29/94 ,  H01L29/66 ,  H01L49/02 ,  H01L23/522

Abstract: An integrated circuit (e.g., a stacked capacitor) achieves higher capacitor density without additional area consumption. The integrated circuit includes a metal-oxide-semiconductor capacitor (MOSCAP), a metal-oxide-metal capacitor (MOMCAP) and a metal-insulator-metal capacitor (MIMCAP) stacked together. The MOSCAP includes a gate and source/drain (S/D) regions. The MOMCAP is included in back-end-of-line (BEOL) layers over the MOSCAP or supported by the MOSCAP.

公开(公告)号：US20190206984A1

公开(公告)日：2019-07-04

申请号：US15860005

申请日：2018-01-02

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Jun CHEN ,  Yangyang SUN ,  Stanley Seungchul SONG ,  Giridhar NALLAPATI

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a substrate, a first group of metal layers including a plurality of first fingers over the substrate, wherein the first fingers are formed without a via. The integrated circuit may further include a second group of metal layers including a plurality of second fingers over the first group of metal layers, wherein the second fingers are formed with vias, and wherein the first and the second group of metal layers are formed by a processing technology node of 7 nm or below.

公开(公告)号：US20190103320A1

公开(公告)日：2019-04-04

申请号：US15723224

申请日：2017-10-03

Applicant: QUALCOMM Incorporated

Inventor： Lixin GE ,  Bin YANG ,  Ye LU ,  Junjing BAO ,  Periannan CHIDAMBARAM

IPC: H01L21/8234 ,  H01L27/06 ,  H01L23/522

Abstract: Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.

公开(公告)号：US20180366413A1

公开(公告)日：2018-12-20

申请号：US15687362

申请日：2017-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Bin YANG ,  Junjing BAO

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  C01B32/182 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823493 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L29/78 ,  H01L29/7851

Abstract: An integrated circuit may include multiple back-end-of-line (BEOL) interconnect layers. The BEOL interconnect layers may include conductive lines and conductive vias. The integrated circuit may further include an interlayer dielectric (ILD) between the BEOL interconnect layers. The ILD may include the conductive lines and the conductive vias. At least a portion of the ILD may include a low-K insulating graphene alloy.

公开(公告)号：US20180342585A1

公开(公告)日：2018-11-29

申请号：US15672017

申请日：2017-08-08

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Junjing BAO ,  Bin YANG ,  Lixin GE ,  Yun YUE

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/72

CPC classification number: H01L29/1606 ,  H01L21/02115 ,  H01L21/02181 ,  H01L21/02271 ,  H01L29/1004 ,  H01L29/1608 ,  H01L29/66037 ,  H01L29/66068 ,  H01L29/6656 ,  H01L29/72 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

公开(公告)号：US20180076139A1

公开(公告)日：2018-03-15

申请号：US15352342

申请日：2016-11-15

Applicant: QUALCOMM Incorporated

Inventor： Yanxiang LIU ,  Haining YANG ,  Youseok SUH ,  Jihong CHOI ,  Junjing BAO

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

公开(公告)号：US20250096139A1

公开(公告)日：2025-03-20

申请号：US18468366

申请日：2023-09-15

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Junjing BAO ,  Giridhar NALLAPATI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed are devices that may incorporate airgaps in top signal layers and/or power layers on a frontside of a substrate. Alternatively, or in addition thereto, airgaps may also be incorporated in signal layers and/or power layers on a backside of the substrate. In this way, metal capacitances of the devices may be reduced, which thereby improves performance of semiconductor circuits such as CPUs.

公开(公告)号：US20240321965A1

公开(公告)日：2024-09-26

申请号：US18189442

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Xia LI ,  Chih-Sung YANG ,  Kwanyong LIM ,  Ming-Huei LIN ,  Hyunwoo PARK ,  Haining YANG

IPC: H01L29/08 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/76841 ,  H01L21/823418 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/6656

Abstract: Disclosed are devices that include a contact for electrical connection with a source/drain. The contact occupies a full width of a contact well other than areas occupied by sidewall spacers. As a result, high resistivity (due to the presence of liners and nucleation layers within the contact well in conventional devices) is reduced or eliminated.