公开(公告)号：US09490424B2

公开(公告)日：2016-11-08

申请号：US15149004

申请日：2016-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Yu Lu

IPC: H01L43/00 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar.

公开(公告)号：US09406875B2

公开(公告)日：2016-08-02

申请号：US14109200

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

Abstract translation: 与收缩装置技术兼容的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共夹层金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

公开(公告)号：US09362336B2

公开(公告)日：2016-06-07

申请号：US14483919

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu

IPC: H01L29/82 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar.

Abstract translation: 一种用于制造磁性隧道结（MTJ）器件的方法包括在第二图案化层内形成凹陷，其中第一图案化层突出于凹陷的第二图案形成层。 这种方法还包括将膜沉积到凹槽中以在沉积的膜内产生锁孔图案。 该方法还包括将锁孔图案通过硬掩模层转移到MTJ堆叠。 该方法还包括将导电材料沉积到转移的锁孔图案中和在MTJ堆叠上。 该方法还包括去除硬掩模层以形成导电硬掩模支柱。

公开(公告)号：US10347821B2

公开(公告)日：2019-07-09

申请号：US15819993

申请日：2017-11-21

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Junjing Bao ,  Xia Li ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L23/544 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

Abstract: A method includes patterning a photo resist layer on top of a semiconductor device. The semiconductor device includes a lower portion, a capping layer formed on top of the lower portion, and an optional oxide layer formed on top of the capping layer. The lower portion includes a dielectric material and an interconnect. The method also includes etching portions of the semiconductor device based on the photo resist layer to expose the interconnect. The method further includes depositing a bottom electrode of a resistive memory device on the interconnect. The bottom electrode is comprised of cobalt tungsten phosphorus (CoWP).

公开(公告)号：US10109674B2

公开(公告)日：2018-10-23

申请号：US14822326

申请日：2015-08-10

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Seung Hyuk Kang

IPC: H01L27/22 ,  H01L23/528 ,  H01L43/12 ,  G06F17/50 ,  H01L23/522 ,  H01L43/02 ,  H01L43/08

Abstract: A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.

公开(公告)号：US09704919B1

公开(公告)日：2017-07-11

申请号：US15192068

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Wei-Chuan Chen ,  Jimmy Jianan Kan ,  Seung Hyuk Kang

IPC: H01L29/66 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L23/528 ,  H01L23/522 ,  H01L43/12 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L27/228 ,  G11C11/16 ,  H01L21/0273 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76879 ,  H01L43/12

Abstract: High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells are disclosed. In one aspect, an exemplary MRAM bit cell includes a coupling column interconnecting an access transistor and a magnetic tunnel junction (MTJ) therein. The coupling column is disposed across a plurality of interconnection layers. In one aspect, the coupling column comprises a high aspect ratio via. In another aspect, the high aspect ratio via is connected directly between a drain contact coupled to a drain of the access transistor and to an end electrode of the MTJ such that no interconnection line and/or interconnection island is provided in the coupling column. In certain aspects, the coupling column may be disposed between an interconnection line and an adjacent interconnection line without increasing an existing interconnection line pitch, thus allowing for a reduction in MRAM bit cell pitch.

公开(公告)号：US09595662B2

公开(公告)日：2017-03-14

申请号：US15213384

申请日：2016-07-18

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

Abstract translation: 与收缩装置技术兼容的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共夹层金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

公开(公告)号：US09514795B1

公开(公告)日：2016-12-06

申请号：US14835871

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Yu Lu ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C11/16

Abstract: Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

公开(公告)号：US20160315248A1

公开(公告)日：2016-10-27

申请号：US14860931

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC classification number: G11C11/1659 ,  G11C11/02 ,  G11C11/161 ,  H01L27/228

Abstract: Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

Abstract translation: 公开了将源极线布局与存取晶体管节点尺寸分离以便于降低接触电阻的磁隧道结（MTJ）存储器位单元。 在一个示例中，提供MTJ存储器位单元，其包括设置在存取晶体管的源极节点的源极触点上方并与之接触的源极板。 源极线设置在源极之上并与源极电接触以将源极线电连接到源极节点。 源极板允许源极线从存取晶体管的源极和漏极触点提供在更高的金属电平，使得源极线不与源极接触物理接触（即，去耦合）。 这允许源极线和漏极列之间的间距从源极和漏极节点的宽度松弛，而不必增加接触电阻。

公开(公告)号：US20160267957A1

公开(公告)日：2016-09-15

申请号：US14645213

申请日：2015-03-11

Applicant: QUALCOMM Incorporated

Inventor： Yu Lu ,  Xia Li

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607

Abstract: A device includes a first magnetic tunnel junction (MTJ) element having a first read margin and a second MTJ element having a second read margin. The first read margin is greater than twice the second read margin. The device also includes an access transistor coupled between the first MTJ element and the second MTJ element. A gate of the access transistor is coupled to a word line. The first MTJ element, the second MTJ element, and the access transistor form a multi-bit spin torque transfer magnetoresistive random access memory (STT-MRAM) memory cell.

Abstract translation: 一种装置包括具有第一读取余量的第一磁性隧道结（MTJ）元件和具有第二读取余量的第二MTJ元件。 第一个读取边距大于第二个读取边距的两倍。 该器件还包括耦合在第一MTJ元件和第二MTJ元件之间的存取晶体管。 存取晶体管的栅极耦合到字线。 第一MTJ元件，第二MTJ元件和存取晶体管形成多位自旋转矩传递磁阻随机存取存储器（STT-MRAM）存储单元。