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21.发明申请公开(公告)号：US20140189457A1
公开(公告)日：2014-07-03
申请号：US13728741
申请日：2012-12-27
IPC分类号： G01R31/3177
CPC分类号： G01R31/31716 , G01R31/3016
摘要： I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.
摘要翻译： 利用片上延迟生成的器件进行I / O延迟测试。 装置的实施例包括I / O缓冲电路，缓冲电路中的至少一个包括被耦合用于缓冲电路的环回测试的发射机和接收机; 以及用于所述至少一个缓冲电路的环回测试的测试电路，所述环回测试包括确定由所述缓冲器电路的发射机发送的测试数据是否与由所述相应耦合的接收机接收的测试数据相匹配。 测试电路包括延迟线，用于从用于测试至少一个缓冲电路的发射时钟信号提供延迟值，提供计数以选择多个延迟值中的一个的计数器， 回测试。
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公开(公告)号：US20140122952A1
公开(公告)日：2014-05-01
申请号：US14145478
申请日：2013-12-31
申请人： David J. Zimmerman
发明人： David J. Zimmerman
IPC分类号： G01R31/3177
CPC分类号： G11C29/32 , G01R31/3177 , G01R31/318513 , G01R31/318558 , G01R31/318572 , G11C5/04 , G11C11/4087 , H01L2924/0002 , H01L2924/00
摘要： A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers, each memory die layer including input-output (I/O) cells and a boundary scan chain for the I/O cells. A boundary scan chain of a memory die layer includes a scan chain portion for each of the I/O cells, the scan chain portion for an I/O cell including a first scan logic multiplexer a scan logic latch, an input of the scan logic latch being coupled with an output of the first scan logic multiplexer, and a decoder to provide command signals to the boundary scan chain.
摘要翻译： 堆叠式存储器的边界扫描链。 存储器件的实施例包括系统元件和包括一个或多个存储管芯层的存储器堆叠，每个存储器管芯层包括用于I / O单元的输入输出（I / O）单元和边界扫描链。 存储芯片层的边界扫描链包括用于每个I / O单元的扫描链部分，用于I / O单元的扫描链部分包括第一扫描逻辑多路复用器，扫描逻辑锁存器，扫描逻辑的输入 锁存器与第一扫描逻辑多路复用器的输出耦合，以及解码器，用于向边界扫描链提供命令信号。
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公开(公告)号：US20140108696A1
公开(公告)日：2014-04-17
申请号：US14132703
申请日：2013-12-18
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G11C5/066 , G11C7/10 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C11/4076 , G11C11/4096
摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
摘要翻译： 实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。 实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器 其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。
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公开(公告)号：US20120120722A1
公开(公告)日：2012-05-17
申请号：US12946612
申请日：2010-11-15
IPC分类号： G11C11/21
CPC分类号： G11C13/0004 , G06F2213/0038 , G11C7/1039 , G11C13/0061 , G11C13/0069
摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
摘要翻译： 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。
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公开(公告)号：US07580465B2
公开(公告)日：2009-08-25
申请号：US11174424
申请日：2005-06-30
CPC分类号： G06F13/28 , G11C5/066 , G11C7/10 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C11/4076 , G11C11/4096
摘要： Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.
摘要翻译： 实施例通过高速串行链路以比高速串行链路常规操作更慢的速度提供对存储器的访问。 实施例可以包括具有耦合到协议识别电路的差分接收器的存储器设备，具有与差分接收器的第一输入端耦合的第一接收器的低速接收电路和与差分接收器的第二输入端耦合的第二接收器 其中低速接收电路与协议识别电路耦合，允许第一和第二接收机以与差分接收机不同的频率访问协议识别块。
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公开(公告)号：US09158619B2
公开(公告)日：2015-10-13
申请号：US13976409
申请日：2012-03-30
IPC分类号： G11C29/00 , G06F11/10 , G11C11/4097 , G11C29/44 , G11C29/04
CPC分类号： G06F11/1016 , G11C11/4097 , G11C29/4401 , G11C2029/0407 , G11C2029/4402
摘要： An apparatus, system, and method provide for on chip redundancy repair for stacked memory devices. A memory device may include a memory stack including one or more layers of dynamic random-access memory (DRAM) and a system element coupled with the memory stack, the system element including a memory controller for control of the memory stack, and repair logic that is coupled with the memory controller. The repair logic is to hold repair addresses that are identified as failing addresses for defective areas of the memory stack, with the repair logic to receive a memory operation request and implement redundancy repair for an operation address for the request using a repair logic memory to store the repair addresses and data for the repair addresses.
摘要翻译： 一种装置，系统和方法提供用于堆叠存储器件的片上冗余修复。 存储器设备可以包括包括一层或多层动态随机存取存储器（DRAM）的存储器堆叠和与存储器堆栈耦合的系统元件，该系统元件包括用于控制存储器堆栈的存储器控制器和修复逻辑， 与存储器控制器耦合。 修复逻辑是保存被识别为存储器堆栈的缺陷区域的故障地址的修复地址，修复逻辑用于接收存储器操作请求，并使用修复逻辑存储器来存储用于该请求的操作地址的冗余修复 修复地址和修复地址的数据。
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公开(公告)号：US08909849B2
公开(公告)日：2014-12-09
申请号：US12946612
申请日：2010-11-15
CPC分类号： G11C13/0004 , G06F2213/0038 , G11C7/1039 , G11C13/0061 , G11C13/0069
摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
摘要翻译： 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。
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28.发明授权Method, system and apparatus for evaluation of input/output buffer circuitry 有权用于评估输入/输出缓冲电路的方法，系统和装置公开(公告)号：US08843794B2
公开(公告)日：2014-09-23
申请号：US13625744
申请日：2012-09-24
IPC分类号： G01R31/28 , G06F11/00 , G06F13/42 , G01R31/00 , G06F13/00 , G01R31/317 , G11C29/02 , G01R31/3187 , G06F11/34 , G11C7/10 , G11C29/12 , H04L1/24 , G01R31/3177 , G01R31/3181 , G11C29/32
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
摘要翻译： 用于评估I / O缓冲电路的技术和机制。 在一个实施例中，对包括I / O缓冲器电路的设备执行测试轮，每个测试轮包括对于每个I / O缓冲器电路的相应回环测试。 每个测试轮对应于发送时钟信号和接收时钟信号之间的不同的相应延迟。 在另一个实施例中，第一测试轮指示至少一个I / O缓冲器电路的故障条件，第二测试轮指示每个I / O缓冲电路的故障条件。 I / O缓冲电路的评估确定装置是否满足测试条件，其中确定是基于与第一测试轮对应的延迟与对应于第二测试轮的延迟之间的差。
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29.发明申请METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY 有权用于评估输入/输出缓冲器电路的方法，系统和装置公开(公告)号：US20140089752A1
公开(公告)日：2014-03-27
申请号：US13625744
申请日：2012-09-24
IPC分类号： G01R31/3177
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
摘要翻译： 用于评估I / O缓冲电路的技术和机制。 在一个实施例中，对包括I / O缓冲器电路的设备执行测试轮，每个测试轮包括对于每个I / O缓冲器电路的相应回环测试。 每个测试轮对应于发送时钟信号和接收时钟信号之间的不同的相应延迟。 在另一个实施例中，第一测试轮指示至少一个I / O缓冲器电路的故障条件，第二测试轮指示每个I / O缓冲电路的故障条件。 I / O缓冲电路的评估确定装置是否满足测试条件，其中确定是基于与第一测试轮对应的延迟与对应于第二测试轮的延迟之间的差。
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公开(公告)号：US20140075107A1
公开(公告)日：2014-03-13
申请号：US14075765
申请日：2013-11-08
IPC分类号： G11C7/22
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。
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