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公开(公告)号：US10133338B2
公开(公告)日：2018-11-20
申请号：US15589651
申请日：2017-05-08
Applicant: RAMBUS INC.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G11C8/00 , G06F1/32 , G06F5/06 , G11C7/10 , G11C11/4093 , G11C11/4076 , G11C7/22 , H03L7/081 , G11C7/04
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US09564879B1
公开(公告)日：2017-02-07
申请号：US14855244
申请日：2015-09-15
Applicant: Rambus Inc.
Inventor： Lei Luo , Barry W. Daly , Kambiz Kaviani , John Cronan Eble, III , John Wilson
CPC classification number: H03K3/013 , G11C5/147 , G11C29/021 , G11C29/022 , G11C29/028 , H04L25/0296 , H04L25/06 , H04L25/08
Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.
Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。
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公开(公告)号：US20160241191A1
公开(公告)日：2016-08-18
申请号：US15049517
申请日：2016-02-22
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Farshid Aryanfar , Kambiz Kaviani
CPC classification number: H03B27/00 , H01F27/006 , H01F27/2804 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B15/00 , H03K5/145 , H03K5/24 , H03K2005/00052
Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.
Abstract translation: 耦合多电感及其应用。 一种装置包括几个电路级。 每个电路级包括与其相邻电路级的电感元件重叠的电感元件，形成耦合电路级的回路。 该装置可以是例如具有彼此磁耦合的多个振荡器的多相振荡器，用于在不同相位产生振荡信号。 该装置也可以是例如用于组合输入信号的相位插值器。
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公开(公告)号：US09136826B2
公开(公告)日：2015-09-15
申请号：US13839059
申请日：2013-03-15
Applicant: Rambus Inc.
Inventor： Kambiz Kaviani , Kashinath Prabhu , Brian Hing-Kit Tsang , Jared L. Zerbe
Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.
Abstract translation: 描述了包括频率变化检测电路的集成电路（IC）的实施例。 一些实施例包括基于第一时钟信号产生第二时钟信号的第一电路，其中第一时钟信号具有第一时钟频率，并且其中第二时钟信号具有作为第一时钟频率的整数倍的第二时钟频率 。 实施例还包括通过使用第二时钟信号过采样第一时钟信号来获得采样的第二电路。 另外，实施例包括基于样本检测第一时钟频率的变化的第三电路。
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公开(公告)号：US20150179248A1
公开(公告)日：2015-06-25
申请号：US14405910
申请日：2013-06-10
Applicant: RAMBUS INC.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G11C11/4076
CPC classification number: G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
Abstract translation: 实施例通常涉及存储器件。 在一个实施例中，存储器件包括时钟接收器电路，其接收外部时钟信号并提供内部时钟信号。 存储装置还包括具有输入的延迟锁定环路电路（DLL）和接收内部时钟信号的电路。 该电路选择内部时钟信号的哪些脉冲被施加到DLL的输入端，使得从外部时钟信号的至少三个连续脉冲中选出的不超过两个时钟脉冲在预定的时间内被施加到DLL的输入 间隔。 在另一个实施例中，一种方法包括在时钟接收器电路处接收外部时钟信号，从时钟接收器电路接收内部时钟信号，以及选择内部时钟信号的哪些脉冲被施加到DLL的输入，其中不再有 从外部时钟信号的至少三个连续脉冲中选择的两个时钟脉冲在预定间隔期间被施加到DLL的输入端。
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Patent Agency Ranking
公开(公告)号：US20220350390A1
公开(公告)日：2022-11-03
申请号：US17748704
申请日：2022-05-19
Applicant: Rambus Inc.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20210041932A1
公开(公告)日：2021-02-11
申请号：US16947973
申请日：2020-08-26
Applicant: Rambus Inc.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US20190171272A1
公开(公告)日：2019-06-06
申请号：US16193247
申请日：2018-11-16
Applicant: RAMBUS INC.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4076 , G06F1/3234 , G06F5/06 , G06F1/3287 , G11C11/4093
CPC classification number: G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US09645631B2
公开(公告)日：2017-05-09
申请号：US15248364
申请日：2016-08-26
Applicant: RAMBUS INC.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
CPC classification number: G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G06F2205/067 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/2272 , H03L7/0816
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
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公开(公告)号：US09432227B2
公开(公告)日：2016-08-30
申请号：US14575985
申请日：2014-12-18
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Kambiz Kaviani , Aliazam Abbasfar
CPC classification number: H04L25/03949 , H03K5/24
Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.
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