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    COMMUNICATION VIA A MEMORY INTERFACE
    21.
    发明申请
    COMMUNICATION VIA A MEMORY INTERFACE 有权
    通过记忆接口通信

    公开(公告)号：US20140082234A1

    公开(公告)日：2014-03-20

    申请号：US14064167

    申请日：2013-10-27

    Applicant: Rambus Inc.

    Inventor： Liji Gopalakrishnan ,  Vlad Fruchter ,  Lawrence Lai ,  Pradeep Batra

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0671 ,  G06F12/06 ,  G06F13/16 ,  G06F13/1621 ,  G06F13/1626 ,  G06F13/1668 ,  G11C7/10

    Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

    Abstract translation: 通过存储器接口连接到存储器控制器的模块的存储器空间可以用作命令缓冲器。 模块通过命令缓冲区接收的命令由模块执行。 存储器控制器可以无序写入命令缓冲器。 存储器控制器可能会延迟或消除对命令缓冲区的写入。 与命令关联的标签用于指定执行顺序命令。 模块的存储空间中的状态缓冲区用于通信是否接收或执行了命令。 通过状态缓冲器接收的信息可以用作确定将命令重新发送到命令缓冲区的基础。

    Memory component with error-detect-correct code interface
    22.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US12130703B2

    公开(公告)日：2024-10-29

    申请号：US18230403

    申请日：2023-08-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: H03M13/27 ,  G06F11/10 ,  H03M13/25 ,  H04L1/00 ,  H04L27/34

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    Memory component with error-detect-correct code interface
    26.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US11487617B2

    公开(公告)日：2022-11-01

    申请号：US17106663

    申请日：2020-11-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: H03M13/27 ,  H04L27/34 ,  H04L1/00 ,  H03M13/25 ,  G06F11/10

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

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