公开(公告)号：US20170053922A1

公开(公告)日：2017-02-23

申请号：US15236472

申请日：2016-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

Abstract translation: 在半导体器件中，存储单元由彼此相邻的控制栅电极和存储栅电极形成，形成在控制栅电极下方的栅绝缘膜和形成在存储栅电极下方并具有电荷累积的绝缘膜 其中的部分。 此外，在该半导体器件中，电容元件由形成在上电极和下电极之间的下电极，上电极和电容绝缘膜形成。 下电极的厚度小于控制栅电极的厚度。

公开(公告)号：US20150236170A1

公开(公告)日：2015-08-20

申请号：US14702238

申请日：2015-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L29/792 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L27/0629 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

Abstract: The performances of a semiconductor device are improved. Between a memory gate electrode and a p type well, and between a control gate electrode and the memory gate electrode of a split gate type nonvolatile memory, an insulation film having a charge accumulation layer therein is formed. The insulation film includes a lamination film of a silicon oxide film, a silicon nitride film formed thereover, another silicon oxide film formed thereover, and an insulation film formed thereover, and thinner than the upper silicon oxide film. The insulation film is in contact with the memory gate electrode including polysilicon. The insulation film is formed of a metal compound containing at least one of Hf, Zr, Al, Ta, and La, and hence can cause Fermi pinning, and has a high dielectric constant.

Abstract translation: 提高了半导体器件的性能。 在存储栅极电极和p型阱之间以及控制栅极电极和分离栅极型非易失性存储器的存储栅极之间形成具有电荷累积层的绝缘膜。 绝缘膜包括氧化硅膜的叠层膜，在其上形成的氮化硅膜，形成在其上的另一个氧化硅膜，以及形成在其上的绝缘膜，并且比上部氧化硅膜薄。 绝缘膜与包括多晶硅的存储栅电极接触。 绝缘膜由包含Hf，Zr，Al，Ta和La中的至少一种的金属化合物形成，因此可以引起费米钉扎，并且具有高介电常数。

公开(公告)号：US20130244391A1

公开(公告)日：2013-09-19

申请号：US13888922

申请日：2013-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L29/66

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

Abstract: An object of the present invention is to provide a semiconductor device having a nonvolatile memory cell of a high operation speed and a high rewrite cycle and a nonvolatile memory cell of high reliability. In a split gate type nonvolatile memory in which memory gate electrodes are formed in the shape of sidewalls of control gate electrodes, it is possible to produce a memory chip having a memory of a high operation speed and a high rewrite cycle and a memory of high reliability at a low cost by jointly loading memory cells having different memory gate lengths in an identical chip.

Abstract translation: 本发明的目的是提供一种具有高操作速度和高重写周期的非易失性存储单元和高可靠性的非易失性存储单元的半导体器件。 在其中存储栅电极形成为控制栅电极的侧壁形状的分离栅型非易失性存储器中，可以产生具有高操作速度和高重写周期的存储器和高存储器的存储芯片 通过在相同的芯片中共同加载具有不同存储器栅极长度的存储单元，以低成本的可靠性。

公开(公告)号：US20130234289A1

公开(公告)日：2013-09-12

申请号：US13867213

申请日：2013-04-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Koichi TOBA ,  Yasushi ISHII ,  Toshikazu MATSUI ,  Takashi HASHIMOTO

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

公开(公告)号：US20240234528A9

公开(公告)日：2024-07-11

申请号：US17969904

申请日：2022-10-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MAEDA ,  Yoshiyuki KAWASHIMA

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/788 ,  H01L29/792

Abstract: A height of an upper surface of a control gate electrode is lower than a highest position of a lower surface of a silicide layer on a memory gate electrode adjacent to the control gate electrode via an ONO film. As a result, a structure in contact with the ONO film between the control gate electrode and the memory gate electrode is only the control gate electrode and the memory gate electrode made of polysilicon.

公开(公告)号：US20230413568A1

公开(公告)日：2023-12-21

申请号：US18303909

申请日：2023-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuhiko SEGI ,  Yoshiyuki KAWASHIMA

IPC: H10B43/35 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B43/40

Abstract: In a memory region, a memory-region first portion in which no raised epitaxial layer is formed, a memory-region second portion in which a first raised epitaxial layer is formed, and a memory-region third portion in which a second raised epitaxial layer is formed are defined. In the memory-region first portion, a first-diffusion-layer first portion of a memory transistor and a second-diffusion-layer first portion of a select transistor are formed. A first-diffusion-layer second portion of the memory transistor is formed in the first raised epitaxial layer. A second-diffusion-layer second portion of the select transistor is formed in the second raised epitaxial layer.

公开(公告)号：US20230275139A1

公开(公告)日：2023-08-31

申请号：US18059603

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/516 ,  H01L29/78391 ,  H01L29/40111 ,  H01L29/6684

Abstract: To improve a reliability of a nonvolatile memory cell including a ferroelectric film. The nonvolatile memory cell MC includes a paraelectric film IL formed on a semiconductor substrate SUB, the ferroelectric film FE formed on the paraelectric film IL, a gate electrode GE formed on the ferroelectric film FE, a high dielectric constant film HK formed on the ferroelectric film FE such that the high dielectric constant film HK cover side surfaces of the gate electrode GE, and a source region SR and a drain region DR formed in an upper surface of the semiconductor substrate SUB such that the ferroelectric film FE is sandwiched between the source region SR and the drain region DR. A relative dielectric constant of the high dielectric constant film HK is higher than a relative dielectric constant of the ferroelectric film FE.

公开(公告)号：US20230268400A1

公开(公告)日：2023-08-24

申请号：US17678460

申请日：2022-02-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L29/40117 ,  H01L29/42344 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/7832 ,  H01L29/792

Abstract: A first gate electrode is formed on a semiconductor substrate via a first insulating film containing a metal element. A sidewall insulating film is formed on a side surface of the first gate electrode. A second gate electrode is formed on the semiconductor substrate via a second insulating film. The second gate electrode is formed so as to adjacent to the first gate electrode via the second insulating film. The second insulating film is made of a stacked film having a third insulating film, a fourth insulating film having a charge accumulating function, and a fifth insulating film. The third insulating film is formed on the semiconductor substrate as a result of an oxidation of a portion of the semiconductor substrate, and formed on the side surface of the first gate electrode as a result of an oxidation of the sidewall insulating film, by the thermal oxidation treatment.

公开(公告)号：US20220157964A1

公开(公告)日：2022-05-19

申请号：US17513404

申请日：2021-10-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiyuki KAWASHIMA ,  Masao INOUE

IPC: H01L29/51 ,  H01L29/792 ,  H01L29/423

Abstract: A memory cell which is a non-volatile memory cell includes a gate insulating film having a charge storage layer capable of retaining charge and a memory gate electrode formed on the gate insulating film. The charge storage layer includes a first insulating film containing hafnium and silicon and a second insulating film formed on the first insulating film and containing hafnium and silicon. Here, a hafnium concentration of the first insulating film is lower than a hafnium concentration of the second insulating film, and a bandgap of the first insulating film is larger than a bandgap of the second insulating film.

公开(公告)号：US20210143260A1

公开(公告)日：2021-05-13

申请号：US17084097

申请日：2020-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Digh HISAMOTO ,  Yoshiyuki KAWASHIMA ,  Takashi HASHIMOTO

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/792 ,  H01L29/10 ,  H01L21/28

Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.