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89 条记录 (耗时 0.037 秒)

    Etch stop layer for etching FinFET gate over a large topography
    21.
    发明授权
    Etch stop layer for etching FinFET gate over a large topography 有权
    蚀刻停止层，用于在大地形上蚀刻FinFET栅极

    公开(公告)号：US06787476B1

    公开(公告)日：2004-09-07

    申请号：US10632989

    申请日：2003-08-04

    申请人： Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Chih-Yuh Yang ,  Bin Yu

    发明人： Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Chih-Yuh Yang ,  Bin Yu

    IPC分类号： H01L21302

    CPC分类号： H01L29/785 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/4908 ,  H01L29/66795

    摘要： A method of forming a gate for a Fin Field Effect Transistor (FinFET) is provided. The method includes forming a first layer of material over a fin and forming a second layer over the first layer. The second layer includes either Ti or TiN. The method further includes forming a third layer over the second layer. The third layer includes an anti-reflective coating. The method also includes etching the first, second and third layers to form the gate for the FinFET.

    摘要翻译： 提供了一种形成Fin场效应晶体管（FinFET）的栅极的方法。 该方法包括在翅片上形成第一层材料，并在第一层上形成第二层。 第二层包括Ti或TiN。 该方法还包括在第二层上形成第三层。 第三层包括抗反射涂层。 该方法还包括蚀刻第一，第二和第三层以形成用于FinFET的栅极。

    Method of making metal gate stack with etch endpoint tracer layer
    23.
    发明授权
    Method of making metal gate stack with etch endpoint tracer layer 有权
    用蚀刻终点示踪层制作金属栅极叠层的方法

    公开(公告)号：US06589858B1

    公开(公告)日：2003-07-08

    申请号：US10163534

    申请日：2002-06-07

    申请人： Srikanteswara Dakshina-Murthy ,  Paul R. Besser

    发明人： Srikanteswara Dakshina-Murthy ,  Paul R. Besser

    IPC分类号： H01L213205

    CPC分类号： H01L21/32136 ,  Y10S438/97

    摘要： A metal gate structure and method of making the same provides a tracer layer over a first metal or metal compound layer. When etching a metal gate, formed of tungsten, for example, with a first etchant chemistry optimized for etching tungsten, detection of the tracer layer through optical emission spectroscopy, for example, indicates the imminent clearing of the tungsten. A second etchant chemistry is then employed that is selective to the first metal or metal compound layer, such as TiN, overlying the gate dielectric. This provides a controlled etching of the TiN and thereby prevents degradation of the underlying gate dielectric material.

    摘要翻译： 金属栅结构及其制造方法在第一金属或金属化合物层上提供示踪层。 当例如用钨蚀刻金属栅极时，例如，用蚀刻钨优化的第一蚀刻剂化学品，例如通过光学发射光谱法检测示踪剂层，表明钨的即将清除。 然后使用对覆盖栅极电介质的第一金属或金属化合物层（例如TiN）具有选择性的第二蚀刻剂化学。 这提供了对TiN的受控蚀刻，从而防止下面的栅介质材料的劣化。

    Method for enhancing shallow trench top corner rounding using endpoint control of nitride layer etch process with appropriate etch front
    24.
    发明授权
    Method for enhancing shallow trench top corner rounding using endpoint control of nitride layer etch process with appropriate etch front 失效
    使用适当蚀刻前沿的氮化物层蚀刻工艺的端点控制来增强浅沟槽顶角圆角的方法

    公开(公告)号：US06579801B1

    公开(公告)日：2003-06-17

    申请号：US09997986

    申请日：2001-11-30

    申请人： Srikanteswara Dakshina-Murthy ,  Christoph Schwan ,  Jeffrey C. Haines

    发明人： Srikanteswara Dakshina-Murthy ,  Christoph Schwan ,  Jeffrey C. Haines

    IPC分类号： H01L21311

    CPC分类号： H01L21/31116 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/76232

    摘要： Various methods of fabricating substrate trenches and isolation structures therein are disclosed. In one aspect, a method of fabricating a trench in a substrate is provided. An oxide/nitride stack is formed on the substrate. An opening with opposing sidewalls is plasma etched in the silicon nitride film until a first portion of the oxide film is exposed while second and third portions of the oxide film positioned on opposite sides of the first portion remain covered by first and second portions of the silicon nitride film that project inwardly from the opposing sidewalls. The oxide film is etched for a selected time period in order to expose a portion of the substrate and to define first and second oxide/nitride ledges that project inwardly from the opposing sidewalls. The substrate is etched to form the trench with the first and second oxide/nitride ledges protecting underlying portions of the substrate.

    摘要翻译： 公开了在其中制造衬底沟槽和隔离结构的各种方法。 一方面，提供了在衬底中制造沟槽的方法。 在基板上形成氧化物/氮化物堆叠。 具有相对的侧壁的开口在氮化硅膜中被等离子体蚀刻，直到氧化膜的第一部分暴露，而位于第一部分的相对侧上的氧化膜的第二和第三部分保持被硅的第一和第二部分覆盖 氮化物膜从相对的侧壁向内突出。 在选择的时间段内蚀刻氧化膜以暴露衬底的一部分并且限定从相对的侧壁向内突出的第一和第二氧化物/氮化物凸缘。 蚀刻衬底以与保护衬底下部的第一和第二氧化物/氮化物凸缘形成沟槽。

    Metal gate stack with etch stop layer
    25.
    发明授权
    Metal gate stack with etch stop layer 失效

    公开(公告)号：US06511911B1

    公开(公告)日：2003-01-28

    申请号：US09824218

    申请日：2001-04-03

    申请人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

    发明人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2144

    CPC分类号： H01L21/28088 ,  H01L29/4966

    摘要： A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

    Semiconductor device with partial passivation layer
    27.
    发明授权
    Semiconductor device with partial passivation layer 有权
    具有部分钝化层的半导体器件

    公开(公告)号：US06313538B1

    公开(公告)日：2001-11-06

    申请号：US09489479

    申请日：2000-01-21

    申请人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    发明人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

    摘要翻译： 半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层 。 一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质 并且与钝化层和第一介电层接触。

    Flash memory device
    30.
    发明授权
    Flash memory device 有权
    闪存设备

    公开(公告)号：US07196372B1

    公开(公告)日：2007-03-27

    申请号：US10614177

    申请日：2003-07-08

    申请人： Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

    发明人： Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L27/11568 ,  H01L29/785

    摘要： A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

    摘要翻译： 非易失性存储器件包括衬底，绝缘层，鳍，氧化物层，间隔物和一个或多个控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 氧化层形成在翅片上并用作存储器件的隧道氧化物。 间隔件邻近翅片的侧表面形成，并且控制栅极邻近间隔件形成。 间隔件用作非易失性存储器件的浮栅电极。