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80 条记录 (耗时 0.043 秒)

    Programmable output buffer
    21.
    发明授权
    Programmable output buffer 有权
    可编程输出缓冲器

    公开(公告)号：US08531205B1

    公开(公告)日：2013-09-10

    申请号：US13363108

    申请日：2012-01-31

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Xiaobao Wang ,  Khai Nguyen ,  Joseph Huang

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0005 ,  H03K19/018585 ,  H03K19/17744 ,  H03K19/17788

    摘要： One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及可编程输出缓冲器，其包括第一和第二可编程可变阻抗单端驱动器电路以及第一和第二终端电路。 第一终端电路耦合到由第一可编程可变阻抗单端驱动电路驱动的第一输出引脚，第二终端电路耦合到由第二可编程可变阻抗单端驱动的第二输出引脚 驱动电路。 第一和第二终端电路是可编程的，以提供用于差分信号的并行终端或者并联终端关断的驱动单端信号。 还公开了其它实施例和特征。

    Multiple data rate interface architecture
    22.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US08098082B1

    公开(公告)日：2012-01-17

    申请号：US12954204

    申请日：2010-11-24

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    Multiple data rate interface architecture
    23.
    发明授权
    Multiple data rate interface architecture 有权
    多数据速率接口架构

    公开(公告)号：US07859304B1

    公开(公告)日：2010-12-28

    申请号：US12329553

    申请日：2008-12-06

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    DQS postamble filtering
    25.
    发明授权
    DQS postamble filtering 失效
    DQS后同步码过滤

    公开(公告)号：US07031222B1

    公开(公告)日：2006-04-18

    申请号：US11046007

    申请日：2005-01-28

    申请人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    发明人： Sanjay K. Charagulla ,  Chiakang Sung ,  Joseph Huang ,  Bonnie I. Wang ,  Yan Chong

    IPC分类号： G11C8/00

    CPC分类号： H03K5/135 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  H03M9/00

    摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

    摘要翻译： 用于在高速数据接口处过滤信号的电路，方法和装置。 一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。 时钟输入端口与输入单元连接或断开。 当接收到数据脉冲串时，时钟输入端口连接到输入单元。 当数据突发结束时，时钟输入端口与输入单元断开连接。 在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。 该信号随后改变指示正在接收最后一个数据位的状态。 当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

    MULTIPLE DATA RATE INTERFACE ARCHITECTURE
    28.
    发明申请
    MULTIPLE DATA RATE INTERFACE ARCHITECTURE 有权
    多种数据速率接口架构

    公开(公告)号：US20120146700A1

    公开(公告)日：2012-06-14

    申请号：US13324354

    申请日：2011-12-13

    申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Bonnie I. Wang

    IPC分类号： H03K5/06

    CPC分类号： H03K19/017581 ,  H03K19/17744

    摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

    摘要翻译： 用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。 本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。 模块化架构便于引脚从一代PLD迁移到下一代。

    PROGRAMMABLE HIGH-SPEED INTERFACE
    29.
    发明申请
    PROGRAMMABLE HIGH-SPEED INTERFACE 有权
    可编程高速接口

    公开(公告)号：US20110227606A1

    公开(公告)日：2011-09-22

    申请号：US13149168

    申请日：2011-05-31

    申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

    IPC分类号： H03K19/0175 ,  H03K3/00

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

    摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES
    30.
    发明申请
    WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES 有权
    可编程逻辑器件中的写层次实现

    公开(公告)号：US20080201597A1

    公开(公告)日：2008-08-21

    申请号：US11843123

    申请日：2007-08-22

    申请人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    发明人： Yan Chong ,  Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Michael H.M. Chu

    IPC分类号： G06F1/12 ,  H04L7/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/222

    摘要： Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

    摘要翻译： 用于存储器接口的电路，方法和装置，其补偿可能由飞越路由拓扑引起的时钟信号和DQ / DQS信号之间的偏差。 通过使用相位延迟时钟信号对DQ / DQS信号进行时钟补偿，其中相位延迟已校准。 在一个示例性校准例程中，向接收设备提供时钟信号。 还提供了DQ / DQS信号，并将其接收的定时进行比较。 DQ / DQS信号的延迟逐渐改变，直到DQ / DQS信号与接收设备的时钟信号对齐。 然后在器件操作期间使用该延迟来延迟提供DQ / DQS信号的寄存器的信号。 每个DQ / DQS组可以与时钟对齐，或者组中的DQS和DQ信号可以独立地对准接收器件上的时钟。