公开(公告)号：US20130126885A1

公开(公告)日：2013-05-23

申请号：US13299254

申请日：2011-11-17

申请人： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

发明人： Donald R. Disney ,  Andrew P. Edwards ,  Hui Nie ,  Richard J. Brown ,  Isik C. Kizilyalli ,  David P. Bour ,  Linda Romano ,  Thomas R. Prunty

IPC分类号： H01L29/20 ,  H01L21/20

CPC分类号： H01L21/761 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/765 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66136 ,  H01L29/66212 ,  H01L29/6631 ,  H01L29/66909 ,  H01L29/8083 ,  H01L29/872

摘要： A method for fabricating an edge termination structure includes providing a substrate having a first surface and a second surface and a first conductivity type, forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate, and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The method also includes implanting ions into a first region of the second GaN epitaxial layer to electrically isolate a second region of the second GaN epitaxial layer from a third region of the second GaN epitaxial layer. The method further includes forming an active device coupled to the second region of the second GaN epitaxial layer and forming the edge termination structure coupled to the third region of the second GaN epitaxial layer.

摘要翻译： 一种用于制造边缘终端结构的方法包括提供具有第一表面和第二表面和第一导电类型的衬底，形成耦合到衬底的第一表面的第一导电类型的第一GaN外延层，并形成第二 与第一导电类型相反的第二导电类型的GaN外延层。 第二GaN外延层耦合到第一GaN外延层。 该方法还包括将离子注入第二GaN外延层的第一区域以将第二GaN外延层的第二区域与第二GaN外延层的第三区域电隔离。 该方法还包括形成耦合到第二GaN外延层的第二区域并形成耦合到第二GaN外延层的第三区域的边缘端接结构的有源器件。

公开(公告)号：US20130126884A1

公开(公告)日：2013-05-23

申请号：US13299227

申请日：2011-11-17

申请人： Linda Romano ,  Andrew P. Edwards ,  Richard J. Brown ,  David P. Bour ,  Hui Nie ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Mahdan Raj

发明人： Linda Romano ,  Andrew P. Edwards ,  Richard J. Brown ,  David P. Bour ,  Hui Nie ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Mahdan Raj

IPC分类号： H01L29/20 ,  H01L21/302 ,  H01L21/20

CPC分类号： H01L29/7787 ,  H01L21/30621 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/872

摘要： A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

摘要翻译： 半导体结构包括具有第一侧和与第一侧相对的第二侧的III族氮化物衬底。 III族氮化物衬底的特征在于第一导电类型和第一掺杂剂浓度。 半导体结构还包括耦合到III族氮化物衬底的第一表面的第一导电类型的III族氮化物外延层和电耦合到III族氮化物衬底的第二表面的第一金属结构。 半导体结构还包括耦合到第一导电类型的III族氮化物外延层的AlGaN外延层和耦合到AlGaN外延层的第二导电类型的III族氮化物外延结构。 III族氮化物外延结构包括至少一个边缘端接结构。

公开(公告)号：US20130075748A1

公开(公告)日：2013-03-28

申请号：US13240877

申请日：2011-09-22

申请人： David P. Bour ,  Richard J. Brown ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Hui Nie ,  Mahdan Raj

发明人： David P. Bour ,  Richard J. Brown ,  Isik C. Kizilyalli ,  Thomas R. Prunty ,  Linda Romano ,  Andrew P. Edwards ,  Hui Nie ,  Mahdan Raj

IPC分类号： H01L29/207 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L21/26546 ,  H01L21/0332 ,  H01L21/2258 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： A method of forming a doped region in a III-nitride substrate includes providing the III-nitride substrate and forming a masking layer having a predetermined pattern and coupled to a portion of the III-nitride substrate. The III-nitride substrate is characterized by a first conductivity type and the predetermined pattern defines exposed regions of the III-nitride substrate. The method also includes heating the III-nitride substrate to a predetermined temperature and placing a dual-precursor gas adjacent the exposed regions of the III-nitride substrate. The dual-precursor gas includes a nitrogen source and a dopant source. The method further includes maintaining the predetermined temperature for a predetermined time period, forming p-type III-nitride regions adjacent the exposed regions of the III-nitride substrate, and removing the masking layer.

公开(公告)号：US20130056743A1

公开(公告)日：2013-03-07

申请号：US13225345

申请日：2011-09-02

申请人： David P. Bour ,  Linda Romano ,  Thomas R. Prunty ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown

发明人： David P. Bour ,  Linda Romano ,  Thomas R. Prunty ,  Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Richard J. Brown

IPC分类号： H01L29/20 ,  H01L21/283

CPC分类号： H01L29/32 ,  H01L21/02389 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/66212 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： A diode includes a substrate characterized by a first dislocation density and a first conductivity type, a first contact coupled to the substrate, and a masking layer having a predetermined thickness and coupled to the semiconductor substrate. The masking layer comprises a plurality of continuous sections and a plurality of openings exposing the substrate and disposed between the continuous sections. The diode also includes an epitaxial layer greater than 5 μm thick coupled to the substrate and the masking layer. The epitaxial layer comprises a first set of regions overlying the plurality of openings and characterized by a second dislocation density and a second set of regions overlying the set of continuous sections and characterized by a third dislocation density less than the first dislocation density and the second dislocation density. The diode further includes a second contact coupled to the epitaxial layer.

公开(公告)号：US20130032812A1

公开(公告)日：2013-02-07

申请号：US13198659

申请日：2011-08-04

申请人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David P. Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L29/808 ,  H01L29/20 ,  H01L21/337

CPC分类号： H01L29/66909 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66924 ,  H01L29/8083

摘要： A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction, and the channel region extends along at least a portion of the second surface of the gate region.

公开(公告)号：US20130127006A1

公开(公告)日：2013-05-23

申请号：US13300028

申请日：2011-11-18

申请人： Madhan Raj ,  Richard J. Brown ,  Thomas R. Prunty ,  David P. Bour ,  lsik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano

发明人： Madhan Raj ,  Richard J. Brown ,  Thomas R. Prunty ,  David P. Bour ,  lsik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano

IPC分类号： H01L29/47 ,  H01L21/20

CPC分类号： H01L29/66143 ,  H01L29/0661 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66212 ,  H01L29/872

摘要： A method for fabricating a III-nitride semiconductor device includes providing a III-nitride substrate having a first surface and a second surface opposing the first surface, forming a III-nitride epitaxial layer coupled to the first surface of the III-nitride substrate, and removing at least a portion of the III-nitride epitaxial layer to form a first exposed surface. The method further includes forming a dielectric layer coupled to the first exposed surface, removing at least a portion of the dielectric layer, and forming a metallic layer coupled to a remaining portion of the dielectric layer such that the remaining portion of the dielectric layer is disposed between the III-nitride epitaxial layer and the metallic layer.

摘要翻译： 一种制造III族氮化物半导体器件的方法包括提供具有第一表面和与第一表面相对的第二表面的III族氮化物衬底，形成耦合到III族氮化物衬底的第一表面的III族氮化物外延层，以及 去除所述III族氮化物外延层的至少一部分以形成第一暴露表面。 该方法还包括形成耦合到第一暴露表面的电介质层，去除电介质层的至少一部分，以及形成耦合到电介质层的剩余部分的金属层，使得电介质层的剩余部分被布置 在III族氮化物外延层和金属层之间。

公开(公告)号：US20120309172A1

公开(公告)日：2012-12-06

申请号：US13118900

申请日：2011-05-31

申请人： Linda T. Romano ,  David P. Bour ,  Richard J. Brown ,  Andrew P. Edwards ,  Isik C. Kizilyalli ,  Hui Nie ,  Thomas R. Prunty

发明人： Linda T. Romano ,  David P. Bour ,  Richard J. Brown ,  Andrew P. Edwards ,  Isik C. Kizilyalli ,  Hui Nie ,  Thomas R. Prunty

IPC分类号： H01L21/20

CPC分类号： H01L21/2654 ,  H01L21/02002 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02664 ,  H01L33/0079

摘要： A method of reusing a III-nitride growth substrate according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor structure on a III-nitride substrate. The III-nitride semiconductor structure includes a sacrificial layer and an additional layer grown over the sacrificial layer. The sacrificial layer is implanted with at least one implant species. The III-nitride substrate is separated from the additional layer at the implanted sacrificial layer. In some embodiments the III-nitride substrate is GaN and the sacrificial layer is GaN, an aluminum-containing III-nitride layer, or an indium-containing III-nitride layer. In some embodiments, the III-nitride substrate is separated from the additional layer by etching the implanted sacrificial layer.

摘要翻译： 根据本发明的实施例的重新使用III族氮化物生长衬底的方法包括在III族氮化物衬底上外延生长III族氮化物半导体结构。 III族氮化物半导体结构包括在牺牲层上生长的牺牲层和附加层。 牺牲层植入至少一种植入物种。 在注入的牺牲层处将III族氮化物衬底与附加层分离。 在一些实施例中，III族氮化物衬底是GaN，牺牲层是GaN，含铝的III族氮化物层或含铟的III族氮化物层。 在一些实施例中，通过蚀刻注入的牺牲层将III族氮化物衬底与附加层分离。

公开(公告)号：US08927999B2

公开(公告)日：2015-01-06

申请号：US13301165

申请日：2011-11-21

申请人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David Bour ,  Richard J. Brown ,  Thomas R. Prunty

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L29/20 ,  H01L21/265 ,  H01L29/66 ,  H01L29/808 ,  H01L29/868 ,  H01L29/872 ,  H01L29/06

CPC分类号： H01L21/2654 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/6631 ,  H01L29/66446 ,  H01L29/66856 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

摘要： An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

摘要翻译： 描述了边缘端接的半导体器件，其包括GaN衬底; 在包括离子注入绝缘区域的GaN衬底上生长的掺杂GaN外延层，其中所述离子注入区域具有至少为最大电阻率的90％的电阻率和诸如肖特金属层的导电层设置在 所述GaN外延层，其中所述导电层与所述离子注入区域的一部分重叠。 使用肖特基接触结构制备肖特基二极管。

公开(公告)号：US20130126888A1

公开(公告)日：2013-05-23

申请号：US13301165

申请日：2011-11-21

申请人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David Bour ,  Richard J. Brown ,  Thomas R. Prunty

发明人： Isik C. Kizilyalli ,  Hui Nie ,  Andrew P. Edwards ,  Linda Romano ,  David Bour ,  Richard J. Brown ,  Thomas R. Prunty

IPC分类号： H01L29/20 ,  H01L21/329

CPC分类号： H01L21/2654 ,  H01L29/0619 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66143 ,  H01L29/6631 ,  H01L29/66446 ,  H01L29/66856 ,  H01L29/8083 ,  H01L29/868 ,  H01L29/872

摘要： An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

摘要翻译： 描述了边缘端接的半导体器件，其包括GaN衬底; 在包括离子注入绝缘区域的GaN衬底上生长的掺杂GaN外延层，其中所述离子注入区域具有至少为最大电阻率的90％的电阻率和诸如肖特金属层的导电层设置在 所述GaN外延层，其中所述导电层与所述离子注入区域的一部分重叠。 使用肖特基接触结构制备肖特基二极管。

公开(公告)号：US20130015552A1

公开(公告)日：2013-01-17

申请号：US13180758

申请日：2011-07-12

申请人： Isik C. Kizilyalli ,  David P. Bour ,  Richard J. Brown ,  Andrew P. Edwards ,  Hui Nie ,  Linda T. Romano

发明人： Isik C. Kizilyalli ,  David P. Bour ,  Richard J. Brown ,  Andrew P. Edwards ,  Hui Nie ,  Linda T. Romano

IPC分类号： H01L29/36 ,  H01L21/761 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L21/761 ,  H01L21/76224 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/861

摘要： Embodiments of the invention include a III-nitride semiconductor layer including a first portion having a first defect density and a second portion having a second defect density. The first defect density is greater than the second defect density. An insulating material is disposed over the first portion. The insulating material is not formed on or is removed from the second portion.

摘要翻译： 本发明的实施例包括具有第一缺陷密度的第一部分和具有第二缺陷密度的第二部分的III族氮化物半导体层。 第一缺陷密度大于第二缺陷密度。 绝缘材料设置在第一部分上。 绝缘材料不形成在第二部分上或从第二部分移除。