公开(公告)号：US07459734B2

公开(公告)日：2008-12-02

申请号：US10846741

申请日：2004-05-14

Applicant: Keith A. Joyner ,  Mark S. Rodder

Inventor： Keith A. Joyner ,  Mark S. Rodder

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

Abstract translation: 一种制造晶体管的方法，包括：提供具有第一表面的半导体层，设置在第一表面上的电介质层，设置在电介质层上的栅电极，与栅电极的至少一部分相邻的绝缘层的晶体管组件， 以及邻近绝缘层的至少一部分的氮化物间隔层。 该方法还包括在第一表面的一部分上沉积将与半导体层反应以形成硅化物并除去未反应材料的材料。 该方法还包括蚀刻氮化物间隔层，沉积与氮化物间隔层的至少一部分相邻的预金属间隔层和至少部分第一表面，蚀刻去除前金属间隔层的一部分以暴露部分 第一表面的硅化部分，并与第一表面的硅化部分形成接触。

公开(公告)号：US07160782B2

公开(公告)日：2007-01-09

申请号：US10870016

申请日：2004-06-17

Applicant: Rick L. Wise ,  Mark S. Rodder

Inventor： Rick L. Wise ,  Mark S. Rodder

IPC: H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/76237 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a substrate (110), the trench having an implanted buffer layer (133) located in the sidewalls thereof. The trench isolation structure (130) further includes a barrier layer (135) located over the implanted buffer layer (133), and fill material (138) located over the barrier layer (135) and substantially filling the trench.

Abstract translation: 本发明提供一种沟槽隔离结构及其制造方法以及包括该沟槽隔离结构的集成电路的制造方法。 在一个实施例中，沟槽隔离结构（130）包括位于衬底（110）内的沟槽，沟槽具有位于其侧壁中的注入缓冲层（133）。 沟槽隔离结构（130）还包括位于注入缓冲层（133）上的阻挡层（135）和位于阻挡层（135）上方并且基本上填充沟槽的填充材料（138）。

公开(公告)号：US06686300B2

公开(公告)日：2004-02-03

申请号：US10055262

申请日：2001-10-25

Applicant: Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

Inventor： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

IPC: H01L21302

CPC classification number: H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

Abstract: A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

公开(公告)号：US06660595B2

公开(公告)日：2003-12-09

申请号：US09839718

申请日：2001-04-20

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L218236

CPC classification number: H01L21/26586 ,  H01L21/823418 ,  Y10S438/982

Abstract: A method of fabricating different transistor structures with the same mask. A masking layer (214) has two openings (204, 202) that expose two transistor areas (304,302). The width of the second opening (202) is adjusted such that the angled implant is substantially blocked from the second transistor area (302). The angled implant forms pocket regions in the first transistor area (304). The same masking layer (214) may then be used to implant source and drain extension regions in both the first and second transistor areas (304, 302).

Abstract translation: 制造具有相同掩模的不同晶体管结构的方法。 掩模层（214）具有暴露两个晶体管区域（304,302）的两个开口（204,202）。 调节第二开口（202）的宽度，使得成角度的植入物基本上被阻挡于第二晶体管区域（302）。 成角度的植入物在第一晶体管区域（304）中形成袋区域。 然后可以使用相同的掩模层（214）来在第一和第二晶体管区域（304,302）中注入源极和漏极延伸区域。

公开(公告)号：US06413824B1

公开(公告)日：2002-07-02

申请号：US09589953

申请日：2000-06-08

Applicant: Amitava Chatterjee ,  Alec J. Morton ,  Mark S. Rodder ,  Taylor R. Efland ,  Chin-Yu Tsai ,  James R. Hellums

Inventor： Amitava Chatterjee ,  Alec J. Morton ,  Mark S. Rodder ,  Taylor R. Efland ,  Chin-Yu Tsai ,  James R. Hellums

IPC: H01L218234

CPC classification number: H01L21/823814 ,  H01L21/823807

Abstract: High performance digital transistors (140) and analog transistors (144) are formed at the same time. The digital transistors (140) include pocket regions (134) for optimum performance. These pocket regions (134) are partially or completely suppressed from at least the drain side of the analog transistors (144) to provide a flat channel doping profile on the drain side. The flat channel doping profile provides high early voltage and higher gain. The suppression is accomplished by using the HVLDD implants for the analog transistors (144).

Abstract translation: 高性能数字晶体管（140）和模拟晶体管（144）同时形成。 数字晶体管（140）包括用于最佳性能的口袋区域（134）。 这些袋区域（134）从模拟晶体管（144）的至少漏极侧部分地或完全被抑制，以在漏极侧提供平坦的沟道掺杂分布。 平坦沟道掺杂分布提供高的早期电压和更高的增益。 通过使用用于模拟晶体管（144）的HVLDD种植体实现抑制。

公开(公告)号：US06246091B1

公开(公告)日：2001-06-12

申请号：US09335242

申请日：1999-06-17

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L2976

CPC classification number: H01L29/0847 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66628

Abstract: A lateral MOSFET (100) and a method for making the same. A two layer raised source/drain region (106) is located adjacent a gate structure (112). The first layer (106a) of the raised source drain is initially doped p-type and the second layer (106b) of the raised source/drain region is doped n-type. P-type dopants from first layer (106a) are diffused into the substrate to form a pocket barrier region (105). N-type dopants from second layer (106b) diffuse into first layer (106a) so that it becomes n-type and into the substrate to form source/drain junction regions (104). P-type pocket barrier region (105) thus provides a barrier between the source/drain junction regions (104) and the channel region (108).

Abstract translation: 横向MOSFET（100）及其制造方法。 两层隆起的源极/漏极区（106）位于栅极结构（112）附近。 凸起的源极漏极的第一层（106a）最初是掺杂p型的，凸起的源极/漏极区的第二层（106b）被掺杂为n型。 来自第一层（106a）的P型掺杂剂扩散到衬底中以形成袋状阻挡区（105）。 来自第二层（106b）的N型掺杂剂扩散到第一层（106a）中，使得其变为n型并进入衬底以形成源极/漏极结区（104）。 因此，P型袋状阻挡区域（105）在源极/漏极结区域（104）和沟道区域（108）之间提供阻挡层。

公开(公告)号：US6083836A

公开(公告)日：2000-07-04

申请号：US216127

申请日：1998-12-18

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L29/786 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/00

CPC classification number: H01L29/66628 ,  H01L21/28079 ,  H01L21/82345 ,  H01L29/41783

Abstract: Transistors may be fabricated by isolating a first region (16) of a semiconductor layer from a second region (18) of the semiconductor layer (12). A first disposable gate structure (26) of the first transistor may be formed over the first region (16) of the semiconductor layer (12). The first disposable gate structure (26) may comprise a replaceable material. A second disposable gate structure (28) of the second complementary transistor may be formed over the second region (18) of the semiconductor layer (12). A replacement layer (70) may be formed over the first disposable gate structure (26). The replacement layer (70) may comprise a replacement material. At least a portion of the replaceable material of the first disposable gate structure (26) may be substitutionally replaced with the replacement material of the replacement layer (70) to form a first gate structure (80).

Abstract translation: 可以通过将半导体层的第一区域（16）与半导体层（12）的第二区域（18）隔离来制造晶体管。 第一晶体管的第一一次性栅极结构（26）可以形成在半导体层（12）的第一区域（16）上。 第一一次性门结构（26）可以包括可更换的材料。 第二互补晶体管的第二一次性栅极结构（28）可以形成在半导体层（12）的第二区域（18）上。 替换层（70）可以形成在第一一次性栅极结构（26）上。 替换层（70）可以包括替换材料。 第一一次性栅极结构（26）的可更换材料的至少一部分可以用替代层（70）的替换材料替代地形成第一栅极结构（80）。

公开(公告)号：US6063675A

公开(公告)日：2000-05-16

申请号：US957193

申请日：1997-10-24

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/66606 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66628 ,  Y10S438/926

Abstract: A method for forming a MOSFET (200) using a disposable gate. A disposable gate (220) having at least two materials that may be etched selectively with respect to each other is formed on a substrate (202). A sidewall dielectric (215) is formed on the sidewalls of the disposable gate (220). The composition of the disposable gate materials (222,223, and 224) and the sidewall dielectric (215) are chosen such that the disposable gate (220) may be removed selectively with respect to the sidewall dielectric (215). A dielectric layer (214) is then deposited over the structure and a portion of the dielectric layer (214) is removed to expose the disposable gate (220) (e.g., using CMP or an etch-back). The composition of the dielectric layer (214) is chosen such that (1) the dielectric layer (214) may be removed selectively with respect to the sidewall dielectric (215) and (2) a layer of the disposable gate (220) may be removed selectively with respect to the dielectric layer (214). The disposable gate (220) is then removed and the gate dielectric (210) and gate electrode (212) are formed.

Abstract translation: 一种使用一次性栅极形成MOSFET（200）的方法。 在衬底（202）上形成具有可相对于彼此选择性蚀刻的至少两种材料的一次性浇口（220）。 侧壁电介质（215）形成在一次性门（220）的侧壁上。 选择一次性栅极材料（222,223和224）和侧壁电介质（215）的组成，使得可以相对于侧壁电介质（215）选择性地移除一次性栅极（220）。 然后在结构上沉积介电层（214），并且去除电介质层（214）的一部分以暴露一次性栅极（220）（例如，使用CMP或蚀刻）。 选择电介质层（214）的组成，使得（1）可以相对于侧壁电介质（215）选择性地去除电介质层（214），和（2）一次性栅极（220）的层可以是 相对于电介质层（214）有选择地移除。 然后去除一次性栅极（220），并形成栅极电介质（210）和栅电极（212）。

公开(公告)号：US4998150A

公开(公告)日：1991-03-05

申请号：US289346

申请日：1988-12-22

Applicant: Mark S. Rodder ,  Richard A. Chapman

Inventor： Mark S. Rodder ,  Richard A. Chapman

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/08

CPC classification number: H01L29/66628 ,  H01L29/0847 ,  Y10S257/90

Abstract: A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

Abstract translation: 提供了一个升高的源极/漏极晶体管，其具有与晶体管栅极（48）相邻的薄的侧壁间隔绝缘体（54）。 第一侧壁间隔物（64）邻近薄侧壁间隔绝缘体（54）和升高的源/漏区（60）设置。 第二侧壁间隔物（66）形成在场绝缘区域（44）和凸起源极/漏极区域（60）之间的界面处。

公开(公告)号：US4877755A

公开(公告)日：1989-10-31

申请号：US200394

申请日：1988-05-31

Applicant: Mark S. Rodder

Inventor： Mark S. Rodder

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/76895 ,  H01L29/4933 ,  Y10S148/019 ,  Y10S148/147

Abstract: A MOS transistor (10) having a thicker silicide layer (50) over a gate (30) than a silicide layer (44) over source and drain regions (42) is disclosed. A process of the present invention forms a first silicide barrier (28) overlying the gate (30) when the gate is formed. Next, a first silicide formation process forms the first silicide layer (44) overlying source and drain regions (42). The silicide barrier layer (28) prevents silicide formation over the gate (30). The silicide barrier (28) is removed, and another silicide barrier (48) is formed over the first silicide layer (44). A second silicide formation process forms the second silicide layer (50) over the gate (30). The silicide barrier layer (48) prevents expansion of the first silicide layer (44).

Abstract translation: 公开了一种MOS晶体管（10），其在源极和漏极区域（42）上的硅化物层（44）上方的栅极（30）上具有较厚的硅化物层（50）。 当形成栅极时，本发明的方法形成了覆盖栅极（30）的第一硅化物屏障（28）。 接下来，第一硅化物形成工艺形成覆盖源区和漏区（42）的第一硅化物层（44）。 硅化物阻挡层（28）防止在栅极（30）上形成硅化物。 除去硅化物阻挡层（28），在第一硅化物层（44）上方形成另一硅化物屏障（48）。 第二硅化物形成工艺在栅极（30）上形成第二硅化物层（50）。 硅化物阻挡层（48）防止第一硅化物层（44）的膨胀。