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    Memory devices with vertical channels
    21.
    发明授权
    Memory devices with vertical channels 有权

    公开(公告)号：US11508730B2

    公开(公告)日：2022-11-22

    申请号：US17032040

    申请日：2020-09-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Jaeho Hong

    IPC: H01L27/108 ,  G11C7/18

    Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

    Semiconductor device
    22.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11469252B2

    公开(公告)日：2022-10-11

    申请号：US16942093

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seok Han Park ,  Yong Seok Kim ,  Hui-Jung Kim ,  Satoru Yamada ,  Kyung Hwan Lee ,  Jae Ho Hong ,  Yoo Sang Hwang

    IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/06 ,  H01L29/45 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02

    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

    SEMICONDUCTOR MEMORY DEVICES
    23.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220278121A1

    公开(公告)日：2022-09-01

    申请号：US17748261

    申请日：2022-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

    IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524

    Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    Semiconductor devices
    24.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11342436B2

    公开(公告)日：2022-05-24

    申请号：US16801508

    申请日：2020-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeho Hong ,  Yongseok Kim ,  Hyuncheol Kim ,  Seokhan Park ,  Satoru Yamada ,  Kyunghwan Lee

    IPC: H01L29/51 ,  H01L29/423 ,  H01L27/108 ,  H01L29/08

    Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.

    SEMICONDUCTOR MEMORY DEVICES
    28.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20200219885A1

    公开(公告)日：2020-07-09

    申请号：US16820006

    申请日：2020-03-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

    Semiconductor device including dummy metal
    30.
    发明授权
    Semiconductor device including dummy metal 有权

    公开(公告)号：US10032780B2

    公开(公告)日：2018-07-24

    申请号：US15139444

    申请日：2016-04-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Min Hee Cho ,  Satoru Yamada ,  Sung-Sam Lee ,  Jung-Bun Lee

    IPC: H01L27/108 ,  H01L23/522

    Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

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