公开(公告)号：US12120882B2

公开(公告)日：2024-10-15

申请号：US17241343

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun Chun ,  Shinhwan Kang ,  Jihwan Kim ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor device includes a lower structure including a peripheral circuit; a stack structure on the lower structure, extending from a memory cell array region to a stepped region, and including a gate stacked region, and an insulator stacked regions arranged in the stepped region in a first direction; a capping insulating structure on the stack structure; and separation structures passing through the gate stacked region. The stack structure includes interlayer insulating layers and horizontal layers, alternately and repeatedly stacked, the horizontal layers include gate horizontal layers and insulating horizontal layers, the gate stacked region includes the gate horizontal layers, each of the insulator stacked regions includes the insulating horizontal layers, in the stepped region, the stack structure includes a first stepped region, a connection stepped region, and a second stepped region.

公开(公告)号：US12096637B2

公开(公告)日：2024-09-17

申请号：US17352862

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Shinhwan Kang ,  Jeehoon Han

IPC: H10B43/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US20220216151A1

公开(公告)日：2022-07-07

申请号：US17537744

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghwan Kim ,  Shinhwan Kang ,  Youngji Noh ,  Jung-Hwan Park ,  Sanghun Chun

IPC: H01L23/535 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.

公开(公告)号：US11289507B2

公开(公告)日：2022-03-29

申请号：US16853047

申请日：2020-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Shinhwan Kang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.

公开(公告)号：US11121151B2

公开(公告)日：2021-09-14

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan Kang ,  Younghwan Son ,  Haemin Lee ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/1157

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US10096616B2

公开(公告)日：2018-10-09

申请号：US15593494

申请日：2017-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/528

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.