公开(公告)号：US10403754B2

公开(公告)日：2019-09-03

申请号：US15970450

申请日：2018-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Sunhom Steve Paak ,  Yeon-Ho Park ,  Dong-Ho Cha

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66

Abstract: Semiconductor devices are provided. A semiconductor device includes a channel. The semiconductor device includes a gate structure having first and second portions. The channel is between the first and second portions of the gate structure. A contact structure is adjacent a portion of a side surface of the channel. Related methods of forming semiconductor devices are also provided.

公开(公告)号：US10128346B2

公开(公告)日：2018-11-13

申请号：US15165145

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun Kim ,  Sung-Dae Suk

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

Abstract: A semiconductor device includes a semiconductor pattern on a substrate along a first direction, a blocking pattern on a top surface of the semiconductor pattern, a first wire pattern on the blocking pattern along a second direction different from the first direction, the first wire including a first part and a second part on opposite sides of the first part, a gate electrode surrounding the first part of the first wire pattern, and a contact surrounding the second part of the first wire pattern, wherein a height of a bottom surface of the contact from a top surface of the substrate is different from a height of a bottom surface of the gate electrode from the top surface of the substrate.

公开(公告)号：US09806194B2

公开(公告)日：2017-10-31

申请号：US14800054

申请日：2015-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a second fin area. A gate structure is disposed on the first fin area. A source region is in contact with the second fin area. The first fin area includes the first material at a first concentration, the second fin area includes the first material at a second concentration which is greater than the first concentration.

公开(公告)号：US09431522B2

公开(公告)日：2016-08-30

申请号：US15003288

申请日：2016-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungmin Kim ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

公开(公告)号：US09362311B1

公开(公告)日：2016-06-07

申请号：US14808027

申请日：2015-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Kang-Ill Seo

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02664 ,  H01L21/02694 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of fabricating a semiconductor device is provided. A first semiconductor layer including Ge at a first concentration is formed on an insulation layer. Second and third semiconductor layers are formed sequentially on the first semiconductor layer. The second and third semiconductor layers include Ge at second and third concentrations higher than the first concentration. A fin type structure is formed by patterning the insulation layer and the first to third semiconductor layers. The fin type structure is vertically protruded. A fin type active pattern is formed on the fin type structure by performing a first thermal process on the fin type structure. The fin type active pattern includes Ge at a fourth concentration higher than the first concentration and lower than the second concentration.

Abstract translation: 提供一种制造半导体器件的方法。 包含第一浓度的Ge的第一半导体层形成在绝缘层上。 在第一半导体层上依次形成第二和第三半导体层。 第二和第三半导体层包括高于第一浓度的第二和第三浓度的Ge。 通过图案化绝缘层和第一至第三半导体层来形成鳍型结构。 鳍型结构垂直突出。 通过对翅片型结构进行第一热处理，在翅片型结构上形成翅片型有源图案。 翅片型有源图案包括比第一浓度高于第二浓度的第四浓度的Ge。

公开(公告)号：US20140335673A1

公开(公告)日：2014-11-13

申请号：US14262937

申请日：2014-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。

公开(公告)号：US20140225198A1

公开(公告)日：2014-08-14

申请号：US13829703

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Hee-Soo Kang ,  Sung-Il Park ,  Sang-Hoon Lee

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823871

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second gate electrodes disposed on the first and second regions, respectively, and first and second source/drain regions disposed on at least one side of the first and second gate electrodes, respectively. The device further includes first and second silicide regions in the first and second source/drain regions, respectively. A contact area between the first silicide region and the first source/drain region is differs in size from a contact area between the second silicide region and the second source/drain region. Methods of fabricating such devices are also provided.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，分别设置在第一和第二区域上的第一和第二栅极电极以及设置在第一和第二栅极的至少一侧上的第一和第二源极/漏极区域 电极。 该器件还分别包括第一和第二源极/漏极区域中的第一和第二硅化物区域。 第一硅化物区域和第一源极/漏极区域之间的接触区域的大小与第二硅化物区域和第二源极/漏极区域之间的接触面积不同。 还提供了制造这种装置的方法。

公开(公告)号：US12255257B2

公开(公告)日：2025-03-18

申请号：US18598672

申请日：2024-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mongsong Liang ,  Sung-Dae Suk ,  Geumjong Bae

IPC: H01L29/786 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

公开(公告)号：US11695009B2

公开(公告)日：2023-07-04

申请号：US17195019

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78696

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.

公开(公告)号：US20210193659A1

公开(公告)日：2021-06-24

申请号：US17195019

申请日：2021-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Jongho Lee ,  Geumjong Bae

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L29/417

Abstract: A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.