公开(公告)号：US20230178425A1

公开(公告)日：2023-06-08

申请号：US18151662

申请日：2023-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Bing ZHOU ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Adarsh RAJASHEKHAR

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76831 ,  H01L21/30608

Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

公开(公告)号：US20220231048A1

公开(公告)日：2022-07-21

申请号：US17150561

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.

公开(公告)号：US20220208600A1

公开(公告)日：2022-06-30

申请号：US17508036

申请日：2021-10-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Monica TITUS ,  Adarsh RAJASHEKHAR

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308

Abstract: A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

公开(公告)号：US20210358952A1

公开(公告)日：2021-11-18

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli ZHANG ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Seung-Yeul YANG

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L23/522 ,  H01L23/528

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210202703A1

公开(公告)日：2021-07-01

申请号：US16728825

申请日：2019-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Rahul SHARANGPANI

IPC: H01L29/417 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597

Abstract: A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, memory openings vertically extending through the alternating stack, vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack, vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines. Each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

公开(公告)号：US20200335516A1

公开(公告)日：2020-10-22

申请号：US16917597

申请日：2020-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11556

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

公开(公告)号：US20180033646A1

公开(公告)日：2018-02-01

申请号：US15730045

申请日：2017-10-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fumitaka AMANO ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Fei ZHOU

IPC: H01L21/443 ,  H01L21/3065 ,  H01L27/108 ,  H01L21/311 ,  H01L27/06 ,  H01L21/768 ,  H01L21/441 ,  H01L29/49 ,  H01L27/105

CPC classification number: H01L27/11563 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/441 ,  H01L21/443 ,  H01L21/76871 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11534 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/495 ,  H01L29/4975

Abstract: Word lines for a three-dimensional memory device can be formed by forming a stack of alternating layers comprising insulating layers and sacrificial material layers and memory stack structures vertically extending therethrough. Backside recesses are formed by removing the sacrificial material layers through a backside via trench. A metal silicide layer and metal portion are formed in the backside recesses to form the word lines including a metal portion, a metal silicide layer, and optionally, a silicon-containing layer.

公开(公告)号：US20240349501A1

公开(公告)日：2024-10-17

申请号：US18363486

申请日：2023-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Bing ZHOU ,  Senaka KANAKAMEDALA

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.

公开(公告)号：US20240349500A1

公开(公告)日：2024-10-17

申请号：US18363460

申请日：2023-08-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bing ZHOU ,  Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.

公开(公告)号：US20240332177A1

公开(公告)日：2024-10-03

申请号：US18362706

申请日：2023-07-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo NAKAMURA ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA

IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.